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| author | David Shah <davey1576@gmail.com> | 2018-06-20 20:14:08 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-06-20 20:14:08 +0200 |
| commit | 93ed8ca40519cc07b4719ea97a32f51d1a5631cb (patch) | |
| tree | 1edddf2071d155b2818dfe3b212db25bdeb9264f /ice40 | |
| parent | c27c96f4f0ec66d13bea7d7cdea25fbeb2e189b7 (diff) | |
| parent | f2ae9a713ba02f8160e64e199ea4203793f6ed90 (diff) | |
| download | nextpnr-93ed8ca40519cc07b4719ea97a32f51d1a5631cb.tar.gz nextpnr-93ed8ca40519cc07b4719ea97a32f51d1a5631cb.tar.bz2 nextpnr-93ed8ca40519cc07b4719ea97a32f51d1a5631cb.zip | |
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.cc | 18 | ||||
| -rw-r--r-- | ice40/chipdb.py | 8 | ||||
| -rw-r--r-- | ice40/main.cc | 19 |
3 files changed, 29 insertions, 16 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index d7673dd0..963b5994 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -306,14 +306,22 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const delay_t Arch::estimateDelay(WireId src, WireId dst) const { assert(src != WireId()); - delay_t x1 = chip_info->wire_data[src.index].x; - delay_t y1 = chip_info->wire_data[src.index].y; + int x1 = chip_info->wire_data[src.index].x; + int y1 = chip_info->wire_data[src.index].y; assert(dst != WireId()); - delay_t x2 = chip_info->wire_data[dst.index].x; - delay_t y2 = chip_info->wire_data[dst.index].y; + int x2 = chip_info->wire_data[dst.index].x; + int y2 = chip_info->wire_data[dst.index].y; - return delay_t(50 * (fabsf(x1 - x2) + fabsf(y1 - y2))); + int xd = x2 - x1, yd = y2 - y1; + int xscale = 120, yscale = 120, offset = 0; + + // if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) { + // yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd); + // offset = 500; + // } + + return xscale * abs(xd) + yscale * abs(yd) + offset; } // ----------------------------------------------------------------------- diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 82b8be8b..fe25c1f1 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -72,10 +72,10 @@ tiletypes["RAMT"] = 4 wiretypes["LOCAL"] = 1 wiretypes["GLOBAL"] = 2 -wiretypes["SP4_VERT"] = 5 -wiretypes["SP4_HORZ"] = 6 -wiretypes["SP12_HORZ"] = 7 -wiretypes["SP12_VERT"] = 8 +wiretypes["SP4_VERT"] = 3 +wiretypes["SP4_HORZ"] = 4 +wiretypes["SP12_HORZ"] = 5 +wiretypes["SP12_VERT"] = 6 def maj_wire_name(name): if name[2].startswith("lutff_"): diff --git a/ice40/main.cc b/ice40/main.cc index d83018ef..8143a902 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -256,15 +256,20 @@ int main(int argc, char *argv[]) for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size()); i++) { delay_t actual_delay; - if (!get_actual_route_delay(&ctx, src_wires[i], dst_wires[i], - actual_delay)) + WireId src = src_wires[i], dst = dst_wires[i]; + if (!get_actual_route_delay(&ctx, src, dst, actual_delay)) continue; - printf("%s %s %.3f %.3f\n", - ctx.getWireName(src_wires[i]).c_str(&ctx), - ctx.getWireName(dst_wires[i]).c_str(&ctx), + printf("%s %s %.3f %.3f %d %d %d %d %d %d\n", + ctx.getWireName(src).c_str(&ctx), + ctx.getWireName(dst).c_str(&ctx), ctx.getDelayNS(actual_delay), - ctx.getDelayNS( - ctx.estimateDelay(src_wires[i], dst_wires[i]))); + ctx.getDelayNS(ctx.estimateDelay(src, dst)), + ctx.chip_info->wire_data[src.index].x, + ctx.chip_info->wire_data[src.index].y, + ctx.chip_info->wire_data[src.index].type, + ctx.chip_info->wire_data[dst.index].x, + ctx.chip_info->wire_data[dst.index].y, + ctx.chip_info->wire_data[dst.index].type); } } |