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authorClifford Wolf <clifford@clifford.at>2018-06-23 15:28:09 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-23 15:28:09 +0200
commita1681560a3c46a0b785c33eddd0038f4fd662675 (patch)
treea413be3374a3fb9bd4cdbd3f10bc970158276810 /ice40
parent04db674b3598a3b124bb7052fa40893111107041 (diff)
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Updates from clangformat
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40')
-rw-r--r--ice40/arch.cc56
-rw-r--r--ice40/arch.h78
-rw-r--r--ice40/main.cc79
3 files changed, 64 insertions, 149 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc
index 78d4c29c..99ea810e 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -122,33 +122,25 @@ PortPin Arch::portPinFromId(IdString type) const
// -----------------------------------------------------------------------
-static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr)
-{
- return ptr->get();
-}
+static const ChipInfoPOD *get_chip_info(const RelPtr<ChipInfoPOD> *ptr) { return ptr->get(); }
Arch::Arch(ArchArgs args) : args(args)
{
#ifdef ICE40_HX1K_ONLY
if (args.type == ArchArgs::HX1K) {
- chip_info = get_chip_info(
- reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
#else
if (args.type == ArchArgs::LP384) {
- chip_info = get_chip_info(
- reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
} else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
- chip_info = get_chip_info(
- reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
} else if (args.type == ArchArgs::UP5K) {
- chip_info = get_chip_info(
- reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
} else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
- chip_info = get_chip_info(
- reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
+ chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
} else {
log_error("Unsupported iCE40 chip type.\n");
}
@@ -228,13 +220,11 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
int x = chip_info->bel_data[bel.index].x;
int y = chip_info->bel_data[bel.index].y;
int start = bel.index, end = bel.index;
- while (start >= 0 && chip_info->bel_data[start].x == x &&
- chip_info->bel_data[start].y == y)
+ while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
start--;
start++;
br.b.cursor = start;
- while (end < chip_info->num_bels && chip_info->bel_data[end].x == x &&
- chip_info->bel_data[end].y == y)
+ while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
end++;
br.e.cursor = end;
return br;
@@ -247,8 +237,7 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
assert(bel != BelId());
int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
- const BelWirePOD *bel_wires =
- chip_info->bel_data[bel.index].bel_wires.get();
+ const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
for (int i = 0; i < num_bel_wires; i++)
if (bel_wires[i].port == pin) {
@@ -305,16 +294,13 @@ IdString Arch::getPipName(PipId pip) const
int x = chip_info->pip_data[pip.index].x;
int y = chip_info->pip_data[pip.index].y;
- std::string src_name =
- chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
+ std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get();
std::replace(src_name.begin(), src_name.end(), '/', '.');
- std::string dst_name =
- chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
+ std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get();
std::replace(dst_name.begin(), dst_name.end(), '/', '.');
- return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" +
- src_name + ".->." + dst_name);
+ return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name);
}
// -----------------------------------------------------------------------
@@ -401,17 +387,14 @@ std::vector<GraphicElement> Arch::getBelGraphics(BelId bel) const
el.type = GraphicElement::G_BOX;
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
el.x2 = chip_info->bel_data[bel.index].x + 0.9;
- el.y1 = chip_info->bel_data[bel.index].y + 0.10 +
- (chip_info->bel_data[bel.index].z) * (0.8 / 8);
- el.y2 = chip_info->bel_data[bel.index].y + 0.18 +
- (chip_info->bel_data[bel.index].z) * (0.8 / 8);
+ el.y1 = chip_info->bel_data[bel.index].y + 0.10 + (chip_info->bel_data[bel.index].z) * (0.8 / 8);
+ el.y2 = chip_info->bel_data[bel.index].y + 0.18 + (chip_info->bel_data[bel.index].z) * (0.8 / 8);
el.z = 0;
ret.push_back(el);
}
if (bel_type == TYPE_SB_IO) {
- if (chip_info->bel_data[bel.index].x == 0 ||
- chip_info->bel_data[bel.index].x == chip_info->width - 1) {
+ if (chip_info->bel_data[bel.index].x == 0 || chip_info->bel_data[bel.index].x == chip_info->width - 1) {
GraphicElement el;
el.type = GraphicElement::G_BOX;
el.x1 = chip_info->bel_data[bel.index].x + 0.1;
@@ -472,12 +455,10 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
// -----------------------------------------------------------------------
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
- IdString toPort, delay_t &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const
{
if (cell->type == id("ICESTORM_LC")) {
- if (fromPort == id("I0") || fromPort == id("I1") ||
- fromPort == id("I2") || fromPort == id("I3")) {
+ if (fromPort == id("I0") || fromPort == id("I1") || fromPort == id("I2") || fromPort == id("I3")) {
if (toPort == id("O") || toPort == id("LO")) {
delay = 450;
return true;
@@ -489,8 +470,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
{
- if (cell->type == id("ICESTORM_LC") &&
- bool_or_default(cell->params, id("DFF_ENABLE"))) {
+ if (cell->type == id("ICESTORM_LC") && bool_or_default(cell->params, id("DFF_ENABLE"))) {
if (port != id("LO") && port != id("CIN") && port != id("COUT"))
return id("CLK");
}
diff --git a/ice40/arch.h b/ice40/arch.h
index 26504cff..f13e3f72 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -98,11 +98,7 @@ template <typename T> struct RelPtr
// reinterpret_cast<const char*>(this);
// }
- const T *get() const
- {
- return reinterpret_cast<const T *>(
- reinterpret_cast<const char *>(this) + offset);
- }
+ const T *get() const { return reinterpret_cast<const T *>(reinterpret_cast<const char *>(this) + offset); }
const T &operator[](size_t index) const { return get()[index]; }
@@ -283,17 +279,12 @@ NEXTPNR_NAMESPACE_END
namespace std {
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelId>
{
- std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const
- noexcept
- {
- return hash<int>()(bel.index);
- }
+ std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX BelId &bel) const noexcept { return hash<int>()(bel.index); }
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
{
- std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const
- noexcept
+ std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX WireId &wire) const noexcept
{
return hash<int>()(wire.index);
}
@@ -301,11 +292,7 @@ template <> struct hash<NEXTPNR_NAMESPACE_PREFIX WireId>
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX PipId>
{
- std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const
- noexcept
- {
- return hash<int>()(pip.index);
- }
+ std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PipId &pip) const noexcept { return hash<int>()(pip.index); }
};
template <> struct hash<NEXTPNR_NAMESPACE_PREFIX BelType> : hash<int>
@@ -337,15 +324,9 @@ struct BelIterator
return prior;
}
- bool operator!=(const BelIterator &other) const
- {
- return cursor != other.cursor;
- }
+ bool operator!=(const BelIterator &other) const { return cursor != other.cursor; }
- bool operator==(const BelIterator &other) const
- {
- return cursor == other.cursor;
- }
+ bool operator==(const BelIterator &other) const { return cursor == other.cursor; }
BelId operator*() const
{
@@ -369,10 +350,7 @@ struct BelPinIterator
const BelPortPOD *ptr = nullptr;
void operator++() { ptr++; }
- bool operator!=(const BelPinIterator &other) const
- {
- return ptr != other.ptr;
- }
+ bool operator!=(const BelPinIterator &other) const { return ptr != other.ptr; }
BelPin operator*() const
{
@@ -397,10 +375,7 @@ struct WireIterator
int cursor = -1;
void operator++() { cursor++; }
- bool operator!=(const WireIterator &other) const
- {
- return cursor != other.cursor;
- }
+ bool operator!=(const WireIterator &other) const { return cursor != other.cursor; }
WireId operator*() const
{
@@ -424,10 +399,7 @@ struct AllPipIterator
int cursor = -1;
void operator++() { cursor++; }
- bool operator!=(const AllPipIterator &other) const
- {
- return cursor != other.cursor;
- }
+ bool operator!=(const AllPipIterator &other) const { return cursor != other.cursor; }
PipId operator*() const
{
@@ -451,10 +423,7 @@ struct PipIterator
const int *cursor = nullptr;
void operator++() { cursor++; }
- bool operator!=(const PipIterator &other) const
- {
- return cursor != other.cursor;
- }
+ bool operator!=(const PipIterator &other) const { return cursor != other.cursor; }
PipId operator*() const
{
@@ -607,8 +576,7 @@ struct Arch : BaseCtx
assert(wire != WireId());
if (chip_info->wire_data[wire.index].bel_uphill.bel_index >= 0) {
- ret.bel.index =
- chip_info->wire_data[wire.index].bel_uphill.bel_index;
+ ret.bel.index = chip_info->wire_data[wire.index].bel_uphill.bel_index;
ret.pin = chip_info->wire_data[wire.index].bel_uphill.port;
}
@@ -620,8 +588,7 @@ struct Arch : BaseCtx
BelPinRange range;
assert(wire != WireId());
range.b.ptr = chip_info->wire_data[wire.index].bels_downhill.get();
- range.e.ptr = range.b.ptr +
- chip_info->wire_data[wire.index].num_bels_downhill;
+ range.e.ptr = range.b.ptr + chip_info->wire_data[wire.index].num_bels_downhill;
return range;
}
@@ -691,8 +658,7 @@ struct Arch : BaseCtx
{
assert(pip != PipId());
assert(pip_to_net[pip.index] == IdString());
- assert(switches_locked[chip_info->pip_data[pip.index].switch_index] ==
- IdString());
+ assert(switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString());
pip_to_net[pip.index] = net;
switches_locked[chip_info->pip_data[pip.index].switch_index] = net;
@@ -709,8 +675,7 @@ struct Arch : BaseCtx
{
assert(pip != PipId());
assert(pip_to_net[pip.index] != IdString());
- assert(switches_locked[chip_info->pip_data[pip.index].switch_index] !=
- IdString());
+ assert(switches_locked[chip_info->pip_data[pip.index].switch_index] != IdString());
WireId dst;
dst.index = chip_info->pip_data[pip.index].dst;
@@ -719,15 +684,13 @@ struct Arch : BaseCtx
nets[pip_to_net[pip.index]]->wires.erase(dst);
pip_to_net[pip.index] = IdString();
- switches_locked[chip_info->pip_data[pip.index].switch_index] =
- IdString();
+ switches_locked[chip_info->pip_data[pip.index].switch_index] = IdString();
}
bool checkPipAvail(PipId pip) const
{
assert(pip != PipId());
- return switches_locked[chip_info->pip_data[pip.index].switch_index] ==
- IdString();
+ return switches_locked[chip_info->pip_data[pip.index].switch_index] == IdString();
}
IdString getBoundPipNet(PipId pip) const
@@ -779,8 +742,7 @@ struct Arch : BaseCtx
PipRange range;
assert(wire != WireId());
range.b.cursor = chip_info->wire_data[wire.index].pips_downhill.get();
- range.e.cursor =
- range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
+ range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_downhill;
return range;
}
@@ -789,8 +751,7 @@ struct Arch : BaseCtx
PipRange range;
assert(wire != WireId());
range.b.cursor = chip_info->wire_data[wire.index].pips_uphill.get();
- range.e.cursor =
- range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
+ range.e.cursor = range.b.cursor + chip_info->wire_data[wire.index].num_uphill;
return range;
}
@@ -832,8 +793,7 @@ struct Arch : BaseCtx
// Get the delay through a cell from one port to another, returning false
// if no path exists
- bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
- delay_t &delay) const;
+ bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const;
// Get the associated clock to a port, or empty if the port is combinational
IdString getPortClock(const CellInfo *cell, IdString port) const;
// Return true if a port is a clock
diff --git a/ice40/main.cc b/ice40/main.cc
index 00ed660f..4047be06 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -52,17 +52,14 @@ void svg_dump_el(const GraphicElement &el)
std::string style = "stroke=\"black\" stroke-width=\"0.1\" fill=\"none\"";
if (el.type == GraphicElement::G_BOX) {
- std::cout << "<rect x=\"" << (offset + scale * el.x1) << "\" y=\""
- << (offset + scale * el.y1) << "\" height=\""
- << (scale * (el.y2 - el.y1)) << "\" width=\""
- << (scale * (el.x2 - el.x1)) << "\" " << style << "/>\n";
+ std::cout << "<rect x=\"" << (offset + scale * el.x1) << "\" y=\"" << (offset + scale * el.y1) << "\" height=\""
+ << (scale * (el.y2 - el.y1)) << "\" width=\"" << (scale * (el.x2 - el.x1)) << "\" " << style
+ << "/>\n";
}
if (el.type == GraphicElement::G_LINE) {
- std::cout << "<line x1=\"" << (offset + scale * el.x1) << "\" y1=\""
- << (offset + scale * el.y1) << "\" x2=\""
- << (offset + scale * el.x2) << "\" y2=\""
- << (offset + scale * el.y2) << "\" " << style << "/>\n";
+ std::cout << "<line x1=\"" << (offset + scale * el.x1) << "\" y1=\"" << (offset + scale * el.y1) << "\" x2=\""
+ << (offset + scale * el.x2) << "\" y2=\"" << (offset + scale * el.y2) << "\" " << style << "/>\n";
}
}
@@ -84,23 +81,17 @@ int main(int argc, char *argv[])
options.add_options()("gui", "start gui");
#endif
options.add_options()("svg", "dump SVG file");
- options.add_options()("pack-only",
- "pack design only without placement or routing");
+ options.add_options()("pack-only", "pack design only without placement or routing");
po::positional_options_description pos;
#ifndef NO_PYTHON
- options.add_options()("run", po::value<std::vector<std::string>>(),
- "python file to execute");
+ options.add_options()("run", po::value<std::vector<std::string>>(), "python file to execute");
pos.add("run", -1);
#endif
- options.add_options()("json", po::value<std::string>(),
- "JSON design file to ingest");
- options.add_options()("pcf", po::value<std::string>(),
- "PCF constraints file to ingest");
- options.add_options()("asc", po::value<std::string>(),
- "asc bitstream file to write");
- options.add_options()("seed", po::value<int>(),
- "seed value for random number generator");
+ options.add_options()("json", po::value<std::string>(), "JSON design file to ingest");
+ options.add_options()("pcf", po::value<std::string>(), "PCF constraints file to ingest");
+ options.add_options()("asc", po::value<std::string>(), "asc bitstream file to write");
+ options.add_options()("seed", po::value<int>(), "seed value for random number generator");
options.add_options()("version,V", "show version");
options.add_options()("tmfuzz", "run path delay estimate fuzzer");
options.add_options()("lp384", "set device type to iCE40LP384");
@@ -109,18 +100,13 @@ int main(int argc, char *argv[])
options.add_options()("hx1k", "set device type to iCE40HX1K");
options.add_options()("hx8k", "set device type to iCE40HX8K");
options.add_options()("up5k", "set device type to iCE40UP5K");
- options.add_options()("freq", po::value<double>(),
- "set target frequency for design in MHz");
+ options.add_options()("freq", po::value<double>(), "set target frequency for design in MHz");
options.add_options()("no-tmdriv", "disable timing-driven placement");
- options.add_options()("package", po::value<std::string>(),
- "set device package");
+ options.add_options()("package", po::value<std::string>(), "set device package");
po::variables_map vm;
try {
- po::parsed_options parsed = po::command_line_parser(argc, argv)
- .options(options)
- .positional(pos)
- .run();
+ po::parsed_options parsed = po::command_line_parser(argc, argv).options(options).positional(pos).run();
po::store(parsed, vm);
@@ -134,18 +120,16 @@ int main(int argc, char *argv[])
if (vm.count("help") || argc == 1) {
help:
- std::cout << boost::filesystem::basename(argv[0])
- << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
std::cout << "\n";
std::cout << options << "\n";
return argc != 1;
}
if (vm.count("version")) {
- std::cout << boost::filesystem::basename(argv[0])
- << " -- Next Generation Place and Route (git "
- "sha1 " GIT_COMMIT_HASH_STR ")\n";
+ std::cout << boost::filesystem::basename(argv[0]) << " -- Next Generation Place and Route (git "
+ "sha1 " GIT_COMMIT_HASH_STR ")\n";
return 1;
}
@@ -237,8 +221,7 @@ int main(int argc, char *argv[])
std::cout << "<svg xmlns=\"http://www.w3.org/2000/svg\" "
"xmlns:xlink=\"http://www.w3.org/1999/xlink\">\n";
for (auto bel : ctx.getBels()) {
- std::cout << "<!-- " << ctx.getBelName(bel).str(&ctx)
- << " -->\n";
+ std::cout << "<!-- " << ctx.getBelName(bel).str(&ctx) << " -->\n";
for (auto &el : ctx.getBelGraphics(bel))
svg_dump_el(el);
}
@@ -273,30 +256,23 @@ int main(int argc, char *argv[])
}
if (ctx.getBelType(b) == TYPE_SB_IO) {
dst_wires.push_back(ctx.getWireBelPin(b, PIN_D_OUT_0));
- dst_wires.push_back(
- ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE));
+ dst_wires.push_back(ctx.getWireBelPin(b, PIN_OUTPUT_ENABLE));
}
}
ctx.shuffle(src_wires);
ctx.shuffle(dst_wires);
- for (int i = 0;
- i < int(src_wires.size()) && i < int(dst_wires.size()); i++) {
+ for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size()); i++) {
delay_t actual_delay;
WireId src = src_wires[i], dst = dst_wires[i];
if (!get_actual_route_delay(&ctx, src, dst, actual_delay))
continue;
- printf("%s %s %.3f %.3f %d %d %d %d %d %d\n",
- ctx.getWireName(src).c_str(&ctx),
- ctx.getWireName(dst).c_str(&ctx),
- ctx.getDelayNS(actual_delay),
- ctx.getDelayNS(ctx.estimateDelay(src, dst)),
- ctx.chip_info->wire_data[src.index].x,
- ctx.chip_info->wire_data[src.index].y,
- ctx.chip_info->wire_data[src.index].type,
- ctx.chip_info->wire_data[dst.index].x,
- ctx.chip_info->wire_data[dst.index].y,
+ printf("%s %s %.3f %.3f %d %d %d %d %d %d\n", ctx.getWireName(src).c_str(&ctx),
+ ctx.getWireName(dst).c_str(&ctx), ctx.getDelayNS(actual_delay),
+ ctx.getDelayNS(ctx.estimateDelay(src, dst)), ctx.chip_info->wire_data[src.index].x,
+ ctx.chip_info->wire_data[src.index].y, ctx.chip_info->wire_data[src.index].type,
+ ctx.chip_info->wire_data[dst.index].x, ctx.chip_info->wire_data[dst.index].y,
ctx.chip_info->wire_data[dst.index].type);
}
}
@@ -339,8 +315,7 @@ int main(int argc, char *argv[])
#ifndef NO_PYTHON
if (vm.count("run")) {
- std::vector<std::string> files =
- vm["run"].as<std::vector<std::string>>();
+ std::vector<std::string> files = vm["run"].as<std::vector<std::string>>();
for (auto filename : files)
execute_python_file(filename.c_str());
}