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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-17 18:58:04 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-20 09:53:35 +0100 |
| commit | ad5f6fccaa4484eb02d3fa6d420ff39517b524e6 (patch) | |
| tree | 84e9ec6bb61da5b8ecacc5429fb9f6084a626861 /machxo2/bitstream.cc | |
| parent | e4fcd3740dd8a650922903db6e15f4eaff25b5ee (diff) | |
| download | nextpnr-ad5f6fccaa4484eb02d3fa6d420ff39517b524e6.tar.gz nextpnr-ad5f6fccaa4484eb02d3fa6d420ff39517b524e6.tar.bz2 nextpnr-ad5f6fccaa4484eb02d3fa6d420ff39517b524e6.zip | |
Use RelSlice, make more in line with ecp5 arch
Diffstat (limited to 'machxo2/bitstream.cc')
| -rw-r--r-- | machxo2/bitstream.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index 232598f3..8cfc408d 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -132,7 +132,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) static void set_pip(Context *ctx, ChipConfig &cc, PipId pip) { std::string tile = ctx->get_pip_tilename(pip); - std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pips_data[pip.index].tile_type].get(); + std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get(); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); @@ -179,13 +179,13 @@ static std::string get_pic_tile(Context *ctx, BelId bel) std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { - return ctx->get_tile_by_type_and_loc(0, bel.location.x, "PIC_T0"); + return ctx->get_tile_by_type_loc(0, bel.location.x, "PIC_T0"); } else if (bel.location.y == ctx->chip_info->height - 1) { - return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PIC_B0"); + return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PIC_B0"); } else if (bel.location.x == 0) { - return ctx->get_tile_by_type_and_loc(bel.location.y, 0, pio_l); + return ctx->get_tile_by_type_loc(bel.location.y, 0, pio_l); } else if (bel.location.x == ctx->chip_info->width - 1) { - return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, pio_r); + return ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, pio_r); } else { NPNR_ASSERT_FALSE("bad PIO location"); } @@ -226,7 +226,7 @@ void write_bitstream(Context *ctx, std::string text_config_file) } BelId bel = ci->bel; if (ci->type == id_FACADE_SLICE) { - std::string tname = ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PLC"); + std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC"); std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get(); NPNR_ASSERT(slice.substr(0, 5) == "SLICE"); |