Merge pull request #747 from cr1901/machxo2

MachXO2 Checkpoint 1

1 files changed, 29 insertions, 2 deletions

diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc
index f7e774cf..ed67975a 100644
--- a/machxo2/bitstream.cc
+++ b/machxo2/bitstream.cc
@@ -71,9 +71,24 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
                 name.find("JINCK") != std::string::npos);
     };
 
-    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix2 == "U_" || prefix2 == "D_" ||
-        prefix7 == "BRANCH_")
+    if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix7 == "BRANCH_")
         return basename;
+
+    if (prefix2 == "U_" || prefix2 == "D_") {
+        // We needded to keep U_ and D_ prefixes to generate the routing
+        // graph connections properly, but in truth they are not relevant
+        // outside of the center row of tiles as far as the database is
+        // concerned. So convert U_/D_ prefixes back to G_ if not in the
+        // center row.
+
+        // FIXME: This is hardcoded to 1200HC coordinates for now. Perhaps
+        // add a center row/col field to chipdb?
+        if (loc.y == 6)
+            return basename;
+        else
+            return "G_" + basename.substr(2);
+    }
+
     if (loc == wire.location) {
         // TODO: JINCK is not currently handled by this.
         if (is_pio_wire(basename)) {
@@ -100,9 +115,21 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
 static void set_pip(Context *ctx, ChipConfig &cc, PipId pip)
 {
     std::string tile = ctx->get_pip_tilename(pip);
+    std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pips_data[pip.index].tile_type].get();
     std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
     std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip));
     cc.tiles[tile].add_arc(sink, source);
+
+    // Special case pips whose config bits are spread across tiles.
+    if (source == "G_PCLKCIBVIQT0" && sink == "G_VPRXCLKI0") {
+        if (tile_type == "CENTER7") {
+            cc.tiles[ctx->get_tile_by_type("CENTER8")].add_arc(sink, source);
+        } else if (tile_type == "CENTER8") {
+            cc.tiles[ctx->get_tile_by_type("CENTER7")].add_arc(sink, source);
+        } else {
+            NPNR_ASSERT_FALSE("Tile does not contain special-cased pip");
+        }
+    }
 }
 
 static std::vector<bool> int_to_bitvector(int val, int size)