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| author | Miodrag Milanovic <mmicko@gmail.com> | 2023-03-17 19:00:05 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-20 09:53:35 +0100 |
| commit | 0ce72e1a3103d52d036f822b98e511d9c4f1e71b (patch) | |
| tree | df69b12dc5ec296cdce6e7e7279234c476f2d811 /machxo2/cells.h | |
| parent | ad5f6fccaa4484eb02d3fa6d420ff39517b524e6 (diff) | |
| download | nextpnr-0ce72e1a3103d52d036f822b98e511d9c4f1e71b.tar.gz nextpnr-0ce72e1a3103d52d036f822b98e511d9c4f1e71b.tar.bz2 nextpnr-0ce72e1a3103d52d036f822b98e511d9c4f1e71b.zip | |
Use TRELLIS primitives
Diffstat (limited to 'machxo2/cells.h')
| -rw-r--r-- | machxo2/cells.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/machxo2/cells.h b/machxo2/cells.h index 7a9bab92..753d7f11 100644 --- a/machxo2/cells.h +++ b/machxo2/cells.h @@ -26,7 +26,7 @@ NEXTPNR_NAMESPACE_BEGIN // When packing DFFs, we need context of how it's connected to a LUT to -// properly map DFF ports to FACADE_SLICEs; DI0 input muxes F0 and OFX0, +// properly map DFF ports to TRELLIS_SLICEs; DI0 input muxes F0 and OFX0, // and a DFF inside a slice can use either DI0 or M0 as an input. enum class LutType { @@ -43,9 +43,9 @@ std::unique_ptr<CellInfo> create_machxo2_cell(Context *ctx, IdString type, std:: inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; } // Return true if a cell is a flipflop -inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_FF; } +inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; } -inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_FACADE_SLICE; } +inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; } // Convert a LUT primitive to (part of) an GENERIC_SLICE, swapping ports // as needed. Set no_dff if a DFF is not being used, so that the output |