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| author | gatecat <gatecat@ds0.me> | 2021-02-15 09:39:56 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-15 09:39:56 +0000 |
| commit | 065f46daeb05a8b12cc663a44410b6da27a8d9e3 (patch) | |
| tree | ca538791141e442c105c47f836069f95ce2f988d /machxo2/examples/blinky.v | |
| parent | 1b6cdce9251d42236a3db0314e84d6a3e3f06408 (diff) | |
| parent | 9c9a02628d60dca9c9a566b0fcf3bf3dd2c68076 (diff) | |
| download | nextpnr-065f46daeb05a8b12cc663a44410b6da27a8d9e3.tar.gz nextpnr-065f46daeb05a8b12cc663a44410b6da27a8d9e3.tar.bz2 nextpnr-065f46daeb05a8b12cc663a44410b6da27a8d9e3.zip | |
Merge pull request #578 from YosysHQ/machxo2-rebase
machxo2, rebased and updated
Diffstat (limited to 'machxo2/examples/blinky.v')
| -rw-r--r-- | machxo2/examples/blinky.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/machxo2/examples/blinky.v b/machxo2/examples/blinky.v new file mode 100644 index 00000000..57bad543 --- /dev/null +++ b/machxo2/examples/blinky.v @@ -0,0 +1,17 @@ +module top(input clk, rst, output [7:0] leds); + +// TODO: Test miter circuit without reset value. SAT and SMT diverge without +// reset value (SAT succeeds, SMT fails). I haven't figured out the correct +// init set of options to make SAT fail. +// "sat -verify -prove-asserts -set-init-def -seq 1 miter" causes assertion +// failure in yosys. +reg [7:0] ctr = 8'h00; +always @(posedge clk) + if (rst) + ctr <= 8'h00; + else + ctr <= ctr + 1'b1; + +assign leds = ctr; + +endmodule |