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| author | gatecat <gatecat@ds0.me> | 2021-02-11 11:10:32 +0000 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-02-12 10:36:59 +0000 |
| commit | 510969ab9704865f87c7c0bd09e0185b729feffc (patch) | |
| tree | 39a6e35998d92f5066f21f8055a17fb7a7428f98 /machxo2/examples/simple_timing.py | |
| parent | c956cae8244c094783edc7101fd0ca542c24e55b (diff) | |
| download | nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.tar.gz nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.tar.bz2 nextpnr-510969ab9704865f87c7c0bd09e0185b729feffc.zip | |
Create machxo2 backend (renamed from generic).
Signed-off-by: William D. Jones <thor0505@comcast.net>
Diffstat (limited to 'machxo2/examples/simple_timing.py')
| -rw-r--r-- | machxo2/examples/simple_timing.py | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/machxo2/examples/simple_timing.py b/machxo2/examples/simple_timing.py new file mode 100644 index 00000000..1067b556 --- /dev/null +++ b/machxo2/examples/simple_timing.py @@ -0,0 +1,13 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="F", delay=ctx.getDelayFromNS(0.2)) |