diff options
| author | gatecat <gatecat@ds0.me> | 2021-10-11 19:35:02 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-10-11 19:35:23 +0100 |
| commit | dd2c5942a4c261fc26b16e19280490a2860020fa (patch) | |
| tree | 9790237518e8a14830dd687fb00ee07dfd47c293 /mistral/arch.h | |
| parent | 349cbdf9da230c04671f7a7bcc2f2ea07f180de4 (diff) | |
| download | nextpnr-dd2c5942a4c261fc26b16e19280490a2860020fa.tar.gz nextpnr-dd2c5942a4c261fc26b16e19280490a2860020fa.tar.bz2 nextpnr-dd2c5942a4c261fc26b16e19280490a2860020fa.zip | |
clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral/arch.h')
| -rw-r--r-- | mistral/arch.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/mistral/arch.h b/mistral/arch.h index 9295692f..4f5e68ae 100644 --- a/mistral/arch.h +++ b/mistral/arch.h @@ -427,10 +427,12 @@ struct Arch : BaseArch<ArchRanges> ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override; - TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override; // delay.cc + TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, + int &clockInfoCount) const override; // delay.cc TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override; // delay.cc - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override; // delay.cc - DelayQuad getPipDelay(PipId pip) const override; // delay.cc + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, + DelayQuad &delay) const override; // delay.cc + DelayQuad getPipDelay(PipId pip) const override; // delay.cc // ------------------------------------------------- |