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| author | gatecat <gatecat@ds0.me> | 2021-06-03 09:04:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-03 09:04:34 +0100 |
| commit | a3d8b4f9d198226ec0903e34a8d290b376b45c0b (patch) | |
| tree | ada2c6a5d48e766fa523e633aaa28179baea3273 /mistral/lab.cc | |
| parent | 589ca8ded5da2012e4388a3ec4c8fae74dff75e4 (diff) | |
| parent | dcbb322447a7fb59cabe197ec1dd2307acfa3681 (diff) | |
| download | nextpnr-a3d8b4f9d198226ec0903e34a8d290b376b45c0b.tar.gz nextpnr-a3d8b4f9d198226ec0903e34a8d290b376b45c0b.tar.bz2 nextpnr-a3d8b4f9d198226ec0903e34a8d290b376b45c0b.zip | |
Merge pull request #718 from YosysHQ/gatecat/hashlib
Moving from unordered_{map, set} to hashlib
Diffstat (limited to 'mistral/lab.cc')
| -rw-r--r-- | mistral/lab.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mistral/lab.cc b/mistral/lab.cc index abd0fec3..56bc604a 100644 --- a/mistral/lab.cc +++ b/mistral/lab.cc @@ -718,7 +718,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm) // - C, E0, and F0 are exclusive to the top LUT5 secion // - D, E1, and F1 are exclusive to the bottom LUT5 section // First find up to two shared inputs - std::unordered_map<IdString, int> shared_nets; + dict<IdString, int> shared_nets; if (luts[0] && luts[1]) { for (int i = 0; i < luts[0]->combInfo.lut_input_count; i++) { for (int j = 0; j < luts[1]->combInfo.lut_input_count; j++) { @@ -826,7 +826,7 @@ void Arch::reassign_alm_inputs(uint32_t lab, uint8_t alm) // This default cell-bel pin mapping is used to provide estimates during placement only. It will have errors and // overlaps and a correct mapping will be resolved twixt placement and routing -const std::unordered_map<IdString, IdString> Arch::comb_pinmap = { +const dict<IdString, IdString> Arch::comb_pinmap = { {id_A, id_F0}, // fastest input first {id_B, id_E0}, {id_C, id_D}, {id_D, id_C}, {id_D0, id_C}, {id_D1, id_B}, {id_E, id_B}, {id_F, id_A}, {id_Q, id_COMBOUT}, {id_SO, id_COMBOUT}, |