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authorgatecat <gatecat@ds0.me>2021-12-11 19:38:14 +0000
committergatecat <gatecat@ds0.me>2021-12-12 13:03:28 +0000
commit78905c3ecf0cc283a79f064bf7e50aa6cdab2743 (patch)
treebba09e41d716647ecbff2cf6b83bbb1271f9cb95 /mistral
parent1c8d4d6460a24251c346f45e94e1d139ef3ac0eb (diff)
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mistral: DATAIN and DATAOUT of GPIO have swapped
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral')
-rw-r--r--mistral/io.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/mistral/io.cc b/mistral/io.cc
index 3a72b001..dab3672e 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -31,9 +31,9 @@ void Arch::create_gpio(int x, int y)
BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
// FIXME: is the port index of zero always correct?
- add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+ add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
- add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
+ add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
bel_data(bel).block_index = z;
}
}