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| author | gatecat <gatecat@ds0.me> | 2021-12-22 13:54:30 +0000 |
|---|---|---|
| committer | Lofty <dan.ravensloft@gmail.com> | 2022-03-09 17:13:54 +0000 |
| commit | da65afc83b83f02efa96e9a7735f7044a1f1e6d1 (patch) | |
| tree | dcf57e53ce35f1c4c2a6ba4171e8ae782fe606f3 /mistral | |
| parent | 78474a5dec13236214c8e15906c40a05ae6ed4af (diff) | |
| download | nextpnr-da65afc83b83f02efa96e9a7735f7044a1f1e6d1.tar.gz nextpnr-da65afc83b83f02efa96e9a7735f7044a1f1e6d1.tar.bz2 nextpnr-da65afc83b83f02efa96e9a7735f7044a1f1e6d1.zip | |
mistral: M10K pack fixes
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'mistral')
| -rw-r--r-- | mistral/arch.cc | 2 | ||||
| -rw-r--r-- | mistral/pack.cc | 18 |
2 files changed, 14 insertions, 6 deletions
diff --git a/mistral/arch.cc b/mistral/arch.cc index 6ba16939..46ed4f62 100644 --- a/mistral/arch.cc +++ b/mistral/arch.cc @@ -410,6 +410,8 @@ void Arch::add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire) void Arch::assign_default_pinmap(CellInfo *cell) { + if (cell->type == id_MISTRAL_M10K) + return; // M10Ks always have a custom pinmap for (auto &port : cell->ports) { auto &pinmap = cell->pin_data[port.first].bel_pins; if (!pinmap.empty()) diff --git a/mistral/pack.cc b/mistral/pack.cc index da1589f0..09fedf10 100644 --- a/mistral/pack.cc +++ b/mistral/pack.cc @@ -384,13 +384,13 @@ struct MistralPacker void setup_m10ks() { - for (auto& cell : ctx->cells) { + for (auto &cell : ctx->cells) { CellInfo *ci = cell.second.get(); if (ci->type != id_MISTRAL_M10K) continue; - auto abits = ci->attrs[id_CFG_ABITS].as_int64(); - auto dbits = ci->attrs[id_CFG_DBITS].as_int64(); + auto abits = ci->params.at(id_CFG_ABITS).as_int64(); + auto dbits = ci->params.at(id_CFG_DBITS).as_int64(); NPNR_ASSERT(abits >= 7 && abits <= 13); NPNR_ASSERT(dbits == 1 || dbits == 2 || dbits == 5 || dbits == 10 || dbits == 20); @@ -417,8 +417,10 @@ struct MistralPacker bit_offset = 1; } for (int bit = bit_offset; bit < abits; bit++) { - ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRA[%d]", bit + addr_offset))}; - ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = {ctx->id(stringf("ADDRB[%d]", bit + addr_offset))}; + ci->pin_data[ctx->id(stringf("A1ADDR[%d]", bit))].bel_pins = { + ctx->id(stringf("ADDRA[%d]", bit + addr_offset))}; + ci->pin_data[ctx->id(stringf("B1ADDR[%d]", bit))].bel_pins = { + ctx->id(stringf("ADDRB[%d]", bit + addr_offset))}; } // Data lines @@ -449,7 +451,10 @@ struct MistralPacker } for (int bit = 0; bit < dbits; bit++) { for (int offset : offsets) { - ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(ctx->id(stringf("DATAAIN[%d]", bit + offset))); + log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))), + ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset)))); + ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back( + ctx->id(stringf("DATAAIN[%d]", bit + offset))); } } @@ -466,6 +471,7 @@ struct MistralPacker pack_io(); constrain_carries(); constrain_lutram(); + setup_m10ks(); } }; }; // namespace |