Replace DelayInfo with DelayPair/DelayQuad

This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>

4 files changed, 29 insertions, 64 deletions

diff --git a/nexus/arch.cc b/nexus/arch.cc
index ff0c269f..9f410758 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -432,7 +432,7 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; };
 
 // -----------------------------------------------------------------------
 
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
     auto lookup_port = [&](IdString p) {
         auto fnd = cell->tmg_portmap.find(p);
@@ -443,8 +443,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
             bool result = lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
             // Because CCU2 = 2x OXIDE_COMB
             if (result && fromPort == id_FCI && toPort == id_FCO) {
-                delay.min_delay /= 2;
-                delay.max_delay /= 2;
+                delay = DelayQuad(delay.minDelay() / 2, delay.maxDelay() / 2);
             }
             return result;
         } else {
@@ -870,7 +869,7 @@ int Arch::get_cell_timing_idx(IdString cell_type, IdString cell_variant) const
             std::make_pair(cell_type.index, cell_variant.index));
 }
 
-bool Arch::lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayInfo &delay) const
+bool Arch::lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayQuad &delay) const
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
@@ -880,13 +879,12 @@ bool Arch::lookup_cell_delay(int type_idx, IdString from_port, IdString to_port,
             std::make_pair(to_port.index, from_port.index));
     if (dly_idx == -1)
         return false;
-    delay.min_delay = ct.prop_delays[dly_idx].min_delay;
-    delay.max_delay = ct.prop_delays[dly_idx].max_delay;
+    delay = DelayQuad(ct.prop_delays[dly_idx].min_delay, ct.prop_delays[dly_idx].max_delay);
     return true;
 }
 
-void Arch::lookup_cell_setuphold(int type_idx, IdString from_port, IdString clock, DelayInfo &setup,
-                                 DelayInfo &hold) const
+void Arch::lookup_cell_setuphold(int type_idx, IdString from_port, IdString clock, DelayPair &setup,
+                                 DelayPair &hold) const
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
@@ -901,8 +899,8 @@ void Arch::lookup_cell_setuphold(int type_idx, IdString from_port, IdString cloc
     hold.max_delay = ct.setup_holds[dly_idx].max_hold;
 }
 
-void Arch::lookup_cell_setuphold_clock(int type_idx, IdString from_port, IdString &clock, DelayInfo &setup,
-                                       DelayInfo &hold) const
+void Arch::lookup_cell_setuphold_clock(int type_idx, IdString from_port, IdString &clock, DelayPair &setup,
+                                       DelayPair &hold) const
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
@@ -916,7 +914,7 @@ void Arch::lookup_cell_setuphold_clock(int type_idx, IdString from_port, IdStrin
     hold.min_delay = ct.setup_holds[dly_idx].min_hold;
     hold.max_delay = ct.setup_holds[dly_idx].max_hold;
 }
-void Arch::lookup_cell_clock_out(int type_idx, IdString to_port, IdString &clock, DelayInfo &delay) const
+void Arch::lookup_cell_clock_out(int type_idx, IdString to_port, IdString &clock, DelayQuad &delay) const
 {
     NPNR_ASSERT(type_idx != -1);
     const auto &ct = speed_grade->cell_types[type_idx];
@@ -925,9 +923,9 @@ void Arch::lookup_cell_clock_out(int type_idx, IdString to_port, IdString &clock
             to_port.index);
     NPNR_ASSERT(dly_idx != -1);
     clock = IdString(ct.prop_delays[dly_idx].from_port);
-    delay.min_delay = ct.prop_delays[dly_idx].min_delay;
-    delay.max_delay = ct.prop_delays[dly_idx].max_delay;
+    delay = DelayQuad(ct.prop_delays[dly_idx].min_delay, ct.prop_delays[dly_idx].max_delay);
 }
+
 TimingPortClass Arch::lookup_port_type(int type_idx, IdString port, PortType dir, IdString clock) const
 {
     if (dir == PORT_IN) {
@@ -940,7 +938,7 @@ TimingPortClass Arch::lookup_port_type(int type_idx, IdString port, PortType dir
                 std::make_pair(port.index, clock.index));
         return (sh_idx != -1) ? TMG_REGISTER_INPUT : TMG_COMB_INPUT;
     } else {
-        DelayInfo dly;
+        DelayQuad dly;
         // If a clock-to-out entry exists, then this is a register output
         return lookup_cell_delay(type_idx, clock, port, dly) ? TMG_REGISTER_OUTPUT : TMG_COMB_OUTPUT;
     }
diff --git a/nexus/arch.h b/nexus/arch.h
index f1332a42..4ccb9870 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1042,13 +1042,7 @@ struct Arch : BaseArch<ArchRanges>
 
     std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId wire) const override;
 
-    DelayInfo getWireDelay(WireId wire) const override
-    {
-        DelayInfo delay;
-        delay.min_delay = 0;
-        delay.max_delay = 0;
-        return delay;
-    }
+    DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
 
     BelPinRange getWireBelPins(WireId wire) const override
     {
@@ -1120,13 +1114,10 @@ struct Arch : BaseArch<ArchRanges>
 
     WireId getPipDstWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).to_wire); }
 
-    DelayInfo getPipDelay(PipId pip) const override
+    DelayQuad getPipDelay(PipId pip) const override
     {
-        DelayInfo delay;
         auto &cls = speed_grade->pip_classes[pip_data(pip).timing_class];
-        delay.min_delay = std::max(0, cls.min_delay);
-        delay.max_delay = std::max(0, cls.max_delay);
-        return delay;
+        return DelayQuad(cls.min_delay, cls.max_delay);
     }
 
     UpDownhillPipRange getPipsDownhill(WireId wire) const override
@@ -1179,13 +1170,7 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getRipupDelayPenalty() const override { return 120; }
     delay_t getWireRipupDelayPenalty(WireId wire) const;
     float getDelayNS(delay_t v) const override { return v * 0.001; }
-    DelayInfo getDelayFromNS(float ns) const override
-    {
-        DelayInfo del;
-        del.min_delay = delay_t(ns * 1000);
-        del.max_delay = delay_t(ns * 1000);
-        return del;
-    }
+    delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
     ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
@@ -1198,7 +1183,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // Get the delay through a cell from one port to another, returning false
     // if no path exists. This only considers combinational delays, as required by the Arch API
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
     // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
     TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
     // Get the TimingClockingInfo of a port
@@ -1385,15 +1370,15 @@ struct Arch : BaseArch<ArchRanges>
     // Given cell type and variant, get the index inside the speed grade timing data
     int get_cell_timing_idx(IdString cell_type, IdString cell_variant = IdString()) const;
     // Return true and set delay if a comb path exists in a given cell timing index
-    bool lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayInfo &delay) const;
+    bool lookup_cell_delay(int type_idx, IdString from_port, IdString to_port, DelayQuad &delay) const;
     // Get setup and hold time for a given cell timing index and signal/clock pair
-    void lookup_cell_setuphold(int type_idx, IdString from_port, IdString clock, DelayInfo &setup,
-                               DelayInfo &hold) const;
+    void lookup_cell_setuphold(int type_idx, IdString from_port, IdString clock, DelayPair &setup,
+                               DelayPair &hold) const;
     // Get setup and hold time and associated clock for a given cell timing index and signal
-    void lookup_cell_setuphold_clock(int type_idx, IdString from_port, IdString &clock, DelayInfo &setup,
-                                     DelayInfo &hold) const;
+    void lookup_cell_setuphold_clock(int type_idx, IdString from_port, IdString &clock, DelayPair &setup,
+                                     DelayPair &hold) const;
     // Similar to lookup_cell_delay but only needs the 'to' signal, intended for clk->out delays
-    void lookup_cell_clock_out(int type_idx, IdString to_port, IdString &clock, DelayInfo &delay) const;
+    void lookup_cell_clock_out(int type_idx, IdString to_port, IdString &clock, DelayQuad &delay) const;
     // Attempt to look up port type based on database
     TimingPortClass lookup_port_type(int type_idx, IdString port, PortType dir, IdString clock) const;
     // -------------------------------------------------
diff --git a/nexus/archdefs.h b/nexus/archdefs.h
index de5e17c8..e6c3edde 100644
--- a/nexus/archdefs.h
+++ b/nexus/archdefs.h
@@ -25,27 +25,6 @@ NEXTPNR_NAMESPACE_BEGIN
 
 typedef int delay_t;
 
-struct DelayInfo
-{
-    delay_t min_delay = 0, max_delay = 0;
-
-    delay_t minRaiseDelay() const { return min_delay; }
-    delay_t maxRaiseDelay() const { return max_delay; }
-
-    delay_t minFallDelay() const { return min_delay; }
-    delay_t maxFallDelay() const { return max_delay; }
-
-    delay_t minDelay() const { return min_delay; }
-    delay_t maxDelay() const { return max_delay; }
-
-    DelayInfo operator+(const DelayInfo &other) const
-    {
-        DelayInfo ret;
-        ret.min_delay = this->min_delay + other.min_delay;
-        ret.max_delay = this->max_delay + other.max_delay;
-        return ret;
-    }
-};
 // https://bugreports.qt.io/browse/QTBUG-80789
 
 #ifndef Q_MOC_RUN
diff --git a/nexus/pack.cc b/nexus/pack.cc
index 4b076e93..af1a921d 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -1862,9 +1862,12 @@ struct NexusPacker
                 return;
             }
             to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-            to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
-            to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
-            to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
+            to->clkconstr->low =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio));
+            to->clkconstr->high =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio));
+            to->clkconstr->period =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio));
             log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);