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| author | myrtle <gatecat@ds0.me> | 2022-09-20 15:55:43 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-20 15:55:43 +0200 |
| commit | f4e6bbd383f6c434c3285fafeb6f73d77fa4f613 (patch) | |
| tree | 1319ce816a7f9e337ba39ae24694bfda2c0ba154 /nexus | |
| parent | 136ab81cbd9cac143987d3d8d1603f13a8353abc (diff) | |
| parent | 9000c41c4b5935d7d03d9d42e9c37b0a9f17fa88 (diff) | |
| download | nextpnr-f4e6bbd383f6c434c3285fafeb6f73d77fa4f613.tar.gz nextpnr-f4e6bbd383f6c434c3285fafeb6f73d77fa4f613.tar.bz2 nextpnr-f4e6bbd383f6c434c3285fafeb6f73d77fa4f613.zip | |
Merge pull request #1019 from antmicro/support-clock-relations
Support cross-domain clock relations in timing analyser
Diffstat (limited to 'nexus')
| -rw-r--r-- | nexus/arch.cc | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/nexus/arch.cc b/nexus/arch.cc index 274c5ad3..5b1e8c16 100644 --- a/nexus/arch.cc +++ b/nexus/arch.cc @@ -526,6 +526,15 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort } int index = get_cell_timing_idx(id_DCS, id_DCS); return lookup_cell_delay(index, fromPort, toPort, delay); + } else if (cell->type == id_DCC) { + if (fromPort == id_CLKI && toPort == id_CLKO) { + // TODO: Use actual DCC delays + delay.rise.min_delay = 1; + delay.rise.max_delay = 1; + delay.fall.min_delay = 1; + delay.fall.max_delay = 1; + return true; + } } return false; } @@ -594,11 +603,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in return type; } else if (cell->type == id_DCC) { if (port == id_CLKI) - return TMG_CLOCK_INPUT; - else if (port == id_CLKO) - return TMG_GEN_CLOCK; - else if (port == id_CE) return TMG_COMB_INPUT; + else if (port == id_CLKO) + return TMG_COMB_OUTPUT; } else if (cell->type == id_DCS) { // FIXME: Making inputs TMG_CLOCK_INPUT and the output TMG_CLOCK_GEN // yielded in error in the timing analyzer. For now keep those as |