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------------------------------------------------------------
-- Copyright (c) 2019 by Paul Scherrer Institute, Switzerland
-- All rights reserved.
------------------------------------------------------------

------------------------------------------------------------
-- Testbench generated by TbGen.py
------------------------------------------------------------
-- see Library/Python/TbGenerator

------------------------------------------------------------
-- Libraries
------------------------------------------------------------
library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	use ieee.math_real.all;

library work;
	use work.psi_common_math_pkg.all;
	use work.psi_common_logic_pkg.all;
	use work.psi_common_i2c_master_pkg.all;

library work;
	use work.psi_tb_compare_pkg.all;
	use work.psi_tb_activity_pkg.all;
	use work.psi_tb_txt_util.all;
	use work.psi_tb_i2c_pkg.all;

------------------------------------------------------------
-- Entity Declaration
------------------------------------------------------------
entity psi_common_i2c_master_tb is
	generic (
		InternalTriState_g : boolean := true
	);
end entity;

------------------------------------------------------------
-- Architecture
------------------------------------------------------------
architecture sim of psi_common_i2c_master_tb is
	-- *** Fixed Generics ***
	constant ClockFrequency_g : real := 125.0e6;
	constant I2cFrequency_g : real := 1.0e6;
	constant BusBusyTimeout_g : real := 50.0e-6;
	constant CmdTimeout_g : real := 10.0e-6;
	
	-- *** Not Assigned Generics (default values) ***
	
	-- *** TB Control ***
	signal TbRunning : boolean := True;
	signal NextCase : integer := -1;
	signal ProcessDone : std_logic_vector(0 to 1) := (others => '0');
	constant AllProcessesDone_c : std_logic_vector(0 to 1) := (others => '1');
	constant TbProcNr_stim_c : integer := 0;
	constant TbProcNr_i2c_c : integer := 1;
	signal StimCase : integer := -1;
	signal I2cCase : integer := -1;
	
	-- *** DUT Signals ***
	signal Clk : std_logic := '1';
	signal Rst : std_logic := '1';
	signal CmdRdy : std_logic := '0';
	signal CmdVld : std_logic := '0';
	signal CmdType : std_logic_vector(2 downto 0) := (others => '0');
	signal CmdData : std_logic_vector(7 downto 0) := (others => '0');
	signal CmdAck : std_logic := '0';
	signal RspVld : std_logic := '0';
	signal RspData : std_logic_vector(7 downto 0) := (others => '0');
	signal RspType : std_logic_vector(2 downto 0) := (others => '0');
	signal RspArbLost : std_logic := '0';
	signal RspAck : std_logic := '0';
	signal RspSeq : std_logic := '0';
	signal BusBusy : std_logic := '0';
	signal TimeoutCmd : std_logic := '0';
	signal I2cScl : std_logic := '0';
	signal I2cSda : std_logic := '0';
	signal I2cScl_I : std_logic := '0';
	signal I2cScl_O : std_logic := '0';
	signal I2cScl_T : std_logic := '0';
	signal I2cSda_I : std_logic := '0';
	signal I2cSda_O : std_logic := '0';
	signal I2cSda_T : std_logic := '0';
	
	-- *** Helper Functions ***
	procedure WaitForCase(	signal TestCase : in integer;
							Value 			: in integer) is
	begin
		if TestCase /= Value then
			wait until TestCase = Value;
		end if;
	end procedure;
	
	procedure ApplyCmd(	Command			: in	std_logic_vector(2 downto 0);
						Data			: in	std_logic_vector(7 downto 0);
						Ack				: in	std_logic;
						signal CmdVld	: out	std_logic;
						signal CmdRdy	: in	std_logic;
						signal CmdType	: out	std_logic_vector(2 downto 0);
						signal CmdData	: out	std_logic_vector(7 downto 0);
						signal CmdAck	: out	std_logic) is
	begin
		wait until rising_edge(Clk);
		CmdVld <= '1';
		CmdType <= Command;
		CmdData <= Data;
		CmdAck  <= Ack;
		wait until rising_edge(Clk) and CmdRdy = '1';
		CmdVld <= '0';
		CmdType	<= (others => '0');
		CmdData <= (others => '0');
		CmdAck  <= '0';
	end procedure;
	
	procedure CheckRsp(	Command				: in	std_logic_vector(2 downto 0);
						Data				: in	std_logic_vector;
						Ack					: in	std_logic;
						ArbLost				: in	std_logic;						
						signal RspVld		: in	std_logic;
						signal RspData		: in	std_logic_vector(7 downto 0);
						signal RspType		: in	std_logic_vector(2 downto 0);
						signal RspArbLost	: in	std_logic;
						signal RspAck		: in	std_logic;
						signal RspSeq		: in	std_logic;
						Msg					: in	string := "No Msg";
						Err					: in	std_logic := '0') is
	begin
		wait until rising_edge(Clk) and RspVld = '1';
		StdlvCompareStdlv(Command, RspType, "Response: Wrong Type - " & Msg);
		if Data /= "X" then
			StdlvCompareStdlv(Data, RspData, "Response: Wrong Data - " & Msg);
		end if;
		if Ack /= 'X' then
			StdlCompare(choose(Ack = '1', 1, 0), RspAck, "Response: Wrong Ack - " & Msg);
		end if;
		if ArbLost /= 'X' then
			StdlCompare(choose(ArbLost = '1', 1, 0), RspArbLost, "Response: Wrong ArbLost - " & Msg);
		end if;		
		StdlCompare(choose(Err = '1', 1, 0), RspSeq, "Response: Wrong Err - " & Msg);
	end procedure;

begin
	------------------------------------------------------------
	-- DUT Instantiation
	------------------------------------------------------------
	i_dut : entity work.psi_common_i2c_master
		generic map (
			ClockFrequency_g => ClockFrequency_g,
			I2cFrequency_g => I2cFrequency_g,
			BusBusyTimeout_g => BusBusyTimeout_g,
			CmdTimeout_g => CmdTimeout_g,
			InternalTriState_g => InternalTriState_g,
			DisableAsserts_g => true
		)
		port map (
			Clk => Clk,
			Rst => Rst,
			CmdRdy => CmdRdy,
			CmdVld => CmdVld,
			CmdType => CmdType,
			CmdData => CmdData,
			CmdAck => CmdAck,
			RspVld => RspVld,
			RspType => RspType,
			RspArbLost => RspArbLost,
			RspData => RspData,
			RspAck => RspAck,
			RspSeq => RspSeq,
			BusBusy => BusBusy,
			TimeoutCmd => TimeoutCmd,
			I2cScl => I2cScl,
			I2cSda => I2cSda,
			I2cScl_I => I2cScl_I,
			I2cScl_O => I2cScl_O,
			I2cScl_T => I2cScl_T,
			I2cSda_I => I2cSda_I,
			I2cSda_O => I2cSda_O,
			I2cSda_T => I2cSda_T
		);
		
	------------------------------------------------------------
	-- I2C Emulation
	------------------------------------------------------------		
	I2cPullup(I2cScl, I2cSda);
	g_triState : if not InternalTriState_g generate
		I2cScl <= 'Z' when I2cScl_T = '1' else I2cScl_O;
		I2cScl_I <= To01X(I2cScl);
		I2cSda <= 'Z' when I2cSda_T = '1' else I2cSda_O;
		I2cSda_I <= To01X(I2cSda);
	end generate;
	
	------------------------------------------------------------
	-- Testbench Control !DO NOT EDIT!
	------------------------------------------------------------
	p_tb_control : process
	begin
		wait until Rst = '0';
		wait until ProcessDone = AllProcessesDone_c;
		TbRunning <= false;
		wait;
	end process;
	
	------------------------------------------------------------
	-- Clocks !DO NOT EDIT!
	------------------------------------------------------------
	p_clock_Clk : process
		constant Frequency_c : real := real(125e6);
	begin
		while TbRunning loop
			wait for 0.5*(1 sec)/Frequency_c;
			Clk <= not Clk;
		end loop;
		wait;
	end process;
	
	
	------------------------------------------------------------
	-- Resets
	------------------------------------------------------------
	p_rst_Rst : process
	begin
		wait for 1 us;
		-- Wait for two clk edges to ensure reset is active for at least one edge
		wait until rising_edge(Clk);
		wait until rising_edge(Clk);
		Rst <= '0';
		wait;
	end process;
	
	
	------------------------------------------------------------
	-- Processes
	------------------------------------------------------------
	-- *** stim ***
	p_stim : process
	begin
		I2cSetFrequency(I2cFrequency_g);
		-- start of process !DO NOT EDIT
		wait until Rst = '0';
		wait until rising_edge(Clk);
		
		-- *** Test Bus Busy ***
		print(">> Test Bus Busy");
		StimCase <= 0;	
		wait until rising_edge(Clk);		
		WaitForCase(I2cCase, 0);
		wait for 10 us;
		
		-- *** Test Start / Repeated-Start / Stop ***
		print(">> Test Start / Repeated-Start / Stop");
		StimCase <= 1;	
		wait until rising_edge(Clk);
		ApplyCmd(CMD_START, 	X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_START, 	"X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
		ApplyCmd(CMD_REPSTART, 	X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_REPSTART, 	"X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start");
		ApplyCmd(CMD_STOP, 		X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_STOP, 		"X", 'X', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop");		
		WaitForCase(I2cCase, 1);
		wait for 10 us;
		
		-- *** Test Write ***
		print(">> Test Write");
		StimCase <= 2;	
		wait until rising_edge(Clk);
		
		-- 1Byte ACK
		ApplyCmd(CMD_START, 	X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_START, 	"X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
		ApplyCmd(CMD_SEND, 		X"A3", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_SEND, 		"X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 1b ACK");
		ApplyCmd(CMD_STOP, 		X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_STOP, 		"X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Stop 1b ACK");			
		
		-- 2Byte ACK, then NACK
		ApplyCmd(CMD_START, 	X"00", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_START, 	"X", 'X', 'X', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK");
		ApplyCmd(CMD_SEND, 		X"12", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);
		CheckRsp(CMD_SEND, 		"X", '1', '0', RspVld, RspData, RspType, RspArbLost, RspAck, RspSeq, "Start 2b ACK -> NACK 1");
		ApplyCmd(CMD_SEND, 		X"34", 'X', CmdVld, CmdRdy, CmdType, CmdData, CmdAck);


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