diff options
| -rw-r--r-- | common/nextpnr.h | 33 | ||||
| -rw-r--r-- | ecp5/arch.h | 6 | ||||
| -rw-r--r-- | generic/arch.h | 6 | ||||
| -rw-r--r-- | ice40/arch.h | 6 |
4 files changed, 33 insertions, 18 deletions
diff --git a/common/nextpnr.h b/common/nextpnr.h index bf3a5c28..856d8993 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -259,6 +259,39 @@ struct BaseCtx delete idstring_str_to_idx; delete idstring_idx_to_str; } + + // -------------------------------------------------------------- + + bool allUiReload = false; + bool frameUiReload = false; + std::unordered_set<BelId> belUiReload; + std::unordered_set<WireId> wireUiReload; + std::unordered_set<PipId> pipUiReload; + + void refreshUi() + { + allUiReload = true; + } + + void refreshUiFrame() + { + frameUiReload = true; + } + + void refreshUiBel(BelId bel) + { + belUiReload.insert(bel); + } + + void refreshUiWire(WireId wire) + { + wireUiReload.insert(wire); + } + + void refreshUiPip(PipId pip) + { + pipUiReload.insert(pip); + } }; NEXTPNR_NAMESPACE_END diff --git a/ecp5/arch.h b/ecp5/arch.h index fc8c1356..ba26682e 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -727,12 +727,6 @@ struct Arch : BaseCtx DecalXY getWireDecal(WireId wire) const; DecalXY getPipDecal(PipId pip) const; - bool allGraphicsReload = false; - bool frameGraphicsReload = false; - std::unordered_set<BelId> belGraphicsReload; - std::unordered_set<WireId> wireGraphicsReload; - std::unordered_set<PipId> pipGraphicsReload; - // ------------------------------------------------- // Get the delay through a cell from one port to another, returning false diff --git a/generic/arch.h b/generic/arch.h index dafbfec3..c73bbf3f 100644 --- a/generic/arch.h +++ b/generic/arch.h @@ -164,12 +164,6 @@ struct Arch : BaseCtx DecalXY getWireDecal(WireId wire) const; DecalXY getPipDecal(PipId pip) const; - bool allGraphicsReload = false; - bool frameGraphicsReload = false; - std::unordered_set<BelId> belGraphicsReload; - std::unordered_set<WireId> wireGraphicsReload; - std::unordered_set<PipId> pipGraphicsReload; - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; IdString getPortClock(const CellInfo *cell, IdString port) const; bool isClockPort(const CellInfo *cell, IdString port) const; diff --git a/ice40/arch.h b/ice40/arch.h index 03685152..28e913e4 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -650,12 +650,6 @@ struct Arch : BaseCtx DecalXY getWireDecal(WireId wire) const; DecalXY getPipDecal(PipId pip) const; - bool allGraphicsReload = false; - bool frameGraphicsReload = false; - std::unordered_set<BelId> belGraphicsReload; - std::unordered_set<WireId> wireGraphicsReload; - std::unordered_set<PipId> pipGraphicsReload; - // ------------------------------------------------- // Get the delay through a cell from one port to another, returning false |