diff options
-rw-r--r-- | common/place_sa.cc | 20 | ||||
-rw-r--r-- | common/place_sa.h | 2 | ||||
-rw-r--r-- | ice40/main.cc | 12 | ||||
-rw-r--r-- | ice40/pack.cc | 2 |
4 files changed, 23 insertions, 13 deletions
diff --git a/common/place_sa.cc b/common/place_sa.cc index 61f9f748..e8b3725c 100644 --- a/common/place_sa.cc +++ b/common/place_sa.cc @@ -74,9 +74,10 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd) { bool all_placed = false; int iters = 25; - while(!all_placed) { + while (!all_placed) { BelId best_bel = BelId(); - float best_score = std::numeric_limits<float>::infinity(), best_ripup_score = std::numeric_limits<float>::infinity(); + float best_score = std::numeric_limits<float>::infinity(), + best_ripup_score = std::numeric_limits<float>::infinity(); Chip &chip = design->chip; CellInfo *ripup_target = nullptr; BelId ripup_bel = BelId(); @@ -86,7 +87,8 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd) } BelType targetType = belTypeFromId(cell->type); for (auto bel : chip.getBels()) { - if (chip.getBelType(bel) == targetType && isValidBelForCell(design, cell, bel)) { + if (chip.getBelType(bel) == targetType && + isValidBelForCell(design, cell, bel)) { if (chip.checkBelAvail(bel)) { float score = random_float_upto(rnd, 1.0); if (score <= best_score) { @@ -97,18 +99,17 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd) float score = random_float_upto(rnd, 1.0); if (score <= best_ripup_score) { best_ripup_score = score; - ripup_target = design->cells.at(chip.getBelCell(bel, true)); + ripup_target = + design->cells.at(chip.getBelCell(bel, true)); ripup_bel = bel; } - } - } } if (best_bel == BelId()) { if (iters == 0 || ripup_bel == BelId()) log_error("failed to place cell '%s' of type '%s'\n", - cell->name.c_str(), cell->type.c_str()); + cell->name.c_str(), cell->type.c_str()); --iters; chip.unbindBel(ripup_target->bel); ripup_target->bel = BelId(); @@ -123,7 +124,6 @@ static void place_initial(Design *design, CellInfo *cell, rnd_state &rnd) cell->attrs["BEL"] = chip.getBelName(cell->bel).str(); cell = ripup_target; } - } // Stores the state of the SA placer @@ -293,7 +293,7 @@ BelId random_bel_for_cell(Design *design, CellInfo *cell, SAState &state, } } -void place_design_sa(Design *design) +void place_design_sa(Design *design, int seed) { SAState state; @@ -329,7 +329,7 @@ void place_design_sa(Design *design) } log_info("place_constraints placed %d\n", int(placed_cells)); rnd_state rnd; - rnd.state = 1; + rnd.state = seed; std::vector<CellInfo *> autoplaced; // Sort to-place cells for deterministic initial placement for (auto cell : design->cells) { diff --git a/common/place_sa.h b/common/place_sa.h index f320111e..944cb97e 100644 --- a/common/place_sa.h +++ b/common/place_sa.h @@ -23,7 +23,7 @@ NEXTPNR_NAMESPACE_BEGIN -extern void place_design_sa(Design *design); +extern void place_design_sa(Design *design, int seed); NEXTPNR_NAMESPACE_END diff --git a/ice40/main.cc b/ice40/main.cc index eb92d92f..c43bffa7 100644 --- a/ice40/main.cc +++ b/ice40/main.cc @@ -82,6 +82,8 @@ int main(int argc, char *argv[]) "PCF constraints file to ingest"); options.add_options()("asc", po::value<std::string>(), "asc bitstream file to write"); + options.add_options()("seed", po::value<int>(), + "seed value for random number generator"); options.add_options()("version,V", "show version"); options.add_options()("lp384", "set device type to iCE40LP384"); options.add_options()("lp1k", "set device type to iCE40LP1K"); @@ -223,8 +225,16 @@ int main(int argc, char *argv[]) pack_design(&design); print_utilisation(&design); + + int seed = 1; + if (vm.count("seed")) { + seed = vm["seed"].as<int>(); + if (seed == 0) + log_error("seed must be non-zero value"); + } + if (!vm.count("pack-only")) { - place_design_sa(&design); + place_design_sa(&design, seed); route_design(&design, verbose); } } diff --git a/ice40/pack.cc b/ice40/pack.cc index 6840d8d1..3e852a91 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -280,7 +280,7 @@ static void insert_global(Design *design, NetInfo *net, bool is_reset, bool is_cen) { std::string glb_name = net->name.str() + std::string("_$glb_") + - (is_reset ? "sr" : (is_cen ? "ce" : "clk")); + (is_reset ? "sr" : (is_cen ? "ce" : "clk")); CellInfo *gb = create_ice_cell(design, "SB_GB", "$gbuf_" + glb_name); gb->ports["USER_SIGNAL_TO_GLOBAL_BUFFER"].net = net; PortRef pr; |