diff options
| -rw-r--r-- | ice40/cells.cc | 6 | ||||
| -rw-r--r-- | ice40/pack_tests/.gitignore | 2 | ||||
| -rw-r--r-- | ice40/pack_tests/ffmodes.v | 8 | ||||
| -rwxr-xr-x | ice40/pack_tests/test.sh | 14 |
4 files changed, 19 insertions, 11 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc index 6ad9d136..d187d492 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -99,16 +99,18 @@ void dff_to_lc(CellInfo *dff, CellInfo *lc, bool pass_thru_lut) if (citer != config.end()) { if ((config.end() - citer) >= 2) { assert(*(citer++) == 'S'); - lc->params["ASYNC_SR"] = "1"; - } else { lc->params["ASYNC_SR"] = "0"; + } else { + lc->params["ASYNC_SR"] = "1"; } if (*citer == 'S') { + citer++; replace_port(dff, "S", lc, "SR"); lc->params["SET_NORESET"] = "1"; } else { assert(*citer == 'R'); + citer++; replace_port(dff, "R", lc, "SR"); lc->params["SET_NORESET"] = "0"; } diff --git a/ice40/pack_tests/.gitignore b/ice40/pack_tests/.gitignore new file mode 100644 index 00000000..749cb303 --- /dev/null +++ b/ice40/pack_tests/.gitignore @@ -0,0 +1,2 @@ +*.vcd +*_out.v diff --git a/ice40/pack_tests/ffmodes.v b/ice40/pack_tests/ffmodes.v index 6ff99bce..c09ced74 100644 --- a/ice40/pack_tests/ffmodes.v +++ b/ice40/pack_tests/ffmodes.v @@ -1,6 +1,10 @@ module top(input clk, cen, rst, ina, inb, output reg outa, outb, outc, outd); reg temp0 = 1'b0, temp1 = 1'b0; +initial outa = 1'b0; +initial outb = 1'b0; +initial outc = 1'b0; +initial outd = 1'b0; always @(posedge clk) if (cen) @@ -17,8 +21,8 @@ always @(negedge clk) temp1 <= inb; -always @(posedge clk or negedge rst) - if(!rst) +always @(posedge clk or posedge rst) + if(rst) outa <= 1'b0; else outa <= temp0; diff --git a/ice40/pack_tests/test.sh b/ice40/pack_tests/test.sh index 24bb6549..7ac3ef76 100755 --- a/ice40/pack_tests/test.sh +++ b/ice40/pack_tests/test.sh @@ -5,11 +5,11 @@ yosys -p "synth_ice40 -nocarry -top io_wrapper; write_json ${NAME}.json" $1 io_w ../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v -yosys -p "rename top gate\ - read_verilog $1\ - rename top gold\ - hierarchy\ - proc\ - clk2fflogic\ - miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter\ +yosys -p "rename chip gate;\ + read_verilog $1;\ + rename top gold;\ + hierarchy;\ + proc;\ + clk2fflogic;\ + miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter;\ sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 20 -seq 10 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v |