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-rw-r--r--common/design_utils.cc4
-rw-r--r--common/nextpnr.h7
-rw-r--r--docs/archapi.md6
-rw-r--r--ecp5/arch.h2
-rw-r--r--fpga_interchange/arch.h3
-rw-r--r--generic/arch.cc5
-rw-r--r--generic/arch.h4
-rw-r--r--generic/arch_pybindings.cc7
-rw-r--r--generic/examples/simple.py4
-rw-r--r--ice40/arch.h2
-rw-r--r--nexus/arch.h2
11 files changed, 30 insertions, 16 deletions
diff --git a/common/design_utils.cc b/common/design_utils.cc
index 16cc2710..b81449b7 100644
--- a/common/design_utils.cc
+++ b/common/design_utils.cc
@@ -71,7 +71,9 @@ void print_utilisation(const Context *ctx)
}
std::map<IdString, int> available_types;
for (auto bel : ctx->getBels()) {
- available_types[ctx->getBelType(bel)]++;
+ if (!ctx->getBelHidden(bel)) {
+ available_types[ctx->getBelType(bel)]++;
+ }
}
log_break();
log_info("Device utilisation:\n");
diff --git a/common/nextpnr.h b/common/nextpnr.h
index c43b9dc4..ddfcc794 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -1089,6 +1089,7 @@ template <typename R> struct ArchAPI : BaseCtx
virtual CellInfo *getBoundBelCell(BelId bel) const = 0;
virtual CellInfo *getConflictingBelCell(BelId bel) const = 0;
virtual IdString getBelType(BelId bel) const = 0;
+ virtual bool getBelHidden(BelId bel) const = 0;
virtual typename R::BelAttrsRangeT getBelAttrs(BelId bel) const = 0;
virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
@@ -1201,7 +1202,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
// Basic config
virtual IdString archId() const override { return this->id(STRINGIFY(ARCHNAME)); }
- virtual IdString archArgsToId(typename R::ArchArgsT args) const { return IdString(); }
+ virtual IdString archArgsToId(typename R::ArchArgsT args) const override { return IdString(); }
virtual int getTilePipDimZ(int x, int y) const override { return 1; }
virtual char getNameDelimiter() const override { return ' '; }
@@ -1228,6 +1229,8 @@ template <typename R> struct BaseArch : ArchAPI<R>
this->refreshUiBel(bel);
}
+ virtual bool getBelHidden(BelId bel) const override { return false; }
+
virtual bool getBelGlobalBuf(BelId bel) const override { return false; }
virtual bool checkBelAvail(BelId bel) const override { return getBoundBelCell(bel) == nullptr; };
virtual CellInfo *getBoundBelCell(BelId bel) const override
@@ -1290,7 +1293,7 @@ template <typename R> struct BaseArch : ArchAPI<R>
virtual NetInfo *getConflictingWireNet(WireId wire) const override { return getBoundWireNet(wire); }
// Pip methods
- virtual IdString getPipType(PipId pip) const { return IdString(); }
+ virtual IdString getPipType(PipId pip) const override { return IdString(); }
virtual typename R::PipAttrsRangeT getPipAttrs(PipId) const override
{
return empty_if_possible<typename R::PipAttrsRangeT>();
diff --git a/docs/archapi.md b/docs/archapi.md
index f6f184e0..3535122e 100644
--- a/docs/archapi.md
+++ b/docs/archapi.md
@@ -225,6 +225,12 @@ Return a list of all bels on the device.
Return the type of a given bel.
+### bool getBelHidden(BelId bel) const
+
+Should this bel be hidden from utilities?
+
+*BaseArch default: returns false*
+
### BelAttrsRangeT getBelAttrs(BelId bel) const
Return the attributes for that bel. Bel attributes are only informal. They are displayed by the GUI but are otherwise
diff --git a/ecp5/arch.h b/ecp5/arch.h
index de8b225e..d5edd88e 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -601,7 +601,7 @@ struct Arch : BaseArch<ArchRanges>
return range;
}
- std::vector<IdString> getBelPins(BelId bel) const;
+ std::vector<IdString> getBelPins(BelId bel) const override;
// -------------------------------------------------
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index fd2d16a2..5964a38f 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -824,8 +824,7 @@ struct Arch : ArchAPI<ArchRanges>
return false;
}
- // TODO: this needs to become part of the Arch API
- bool getBelHidden(BelId bel) const { return bel_info(chip_info, bel).category != BEL_CATEGORY_LOGIC; }
+ bool getBelHidden(BelId bel) const override { return bel_info(chip_info, bel).category != BEL_CATEGORY_LOGIC; }
IdString getBelType(BelId bel) const override
{
diff --git a/generic/arch.cc b/generic/arch.cc
index 912f8a53..b54a8b65 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -91,7 +91,7 @@ void Arch::addPip(IdStringList name, IdString type, IdStringList srcWire, IdStri
tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
}
-void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
+void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden)
{
NPNR_ASSERT(bels.count(name) == 0);
NPNR_ASSERT(bel_by_loc.count(loc) == 0);
@@ -102,6 +102,7 @@ void Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb)
bi.y = loc.y;
bi.z = loc.z;
bi.gb = gb;
+ bi.hidden = hidden;
bel_ids.push_back(name);
bel_by_loc[loc] = name;
@@ -319,6 +320,8 @@ const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
IdString Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
+bool Arch::getBelHidden(BelId bel) const { return bels.at(bel).hidden; }
+
const std::map<IdString, std::string> &Arch::getBelAttrs(BelId bel) const { return bels.at(bel).attrs; }
WireId Arch::getBelPinWire(BelId bel, IdString pin) const
diff --git a/generic/arch.h b/generic/arch.h
index 09fd8e34..accf2dce 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -77,6 +77,7 @@ struct BelInfo
DecalXY decalxy;
int x, y, z;
bool gb;
+ bool hidden;
};
struct GroupInfo
@@ -177,7 +178,7 @@ struct Arch : ArchAPI<ArchRanges>
void addWire(IdStringList name, IdString type, int x, int y);
void addPip(IdStringList name, IdString type, IdStringList srcWire, IdStringList dstWire, DelayInfo delay, Loc loc);
- void addBel(IdStringList name, IdString type, Loc loc, bool gb);
+ void addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidden);
void addBelInput(IdStringList bel, IdString name, IdStringList wire);
void addBelOutput(IdStringList bel, IdString name, IdStringList wire);
void addBelInout(IdStringList bel, IdString name, IdStringList wire);
@@ -237,6 +238,7 @@ struct Arch : ArchAPI<ArchRanges>
CellInfo *getConflictingBelCell(BelId bel) const override;
const std::vector<BelId> &getBels() const override;
IdString getBelType(BelId bel) const override;
+ bool getBelHidden(BelId bel) const override;
const std::map<IdString, std::string> &getBelAttrs(BelId bel) const override;
WireId getBelPinWire(BelId bel, IdString pin) const override;
PortType getBelPinType(BelId bel, IdString pin) const override;
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index 29e8bc53..3dc04206 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -162,10 +162,9 @@ void arch_wrap_python(py::module &m)
pass_through<DelayInfo>, pass_through<Loc>>::def_wrap(ctx_cls, "addPip", "name"_a, "type"_a,
"srcWire"_a, "dstWire"_a, "delay"_a, "loc"_a);
- fn_wrapper_4a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
- conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>>::def_wrap(ctx_cls, "addBel",
- "name"_a, "type"_a,
- "loc"_a, "gb"_a);
+ fn_wrapper_5a_v<Context, decltype(&Context::addBel), &Context::addBel, conv_from_str<IdStringList>,
+ conv_from_str<IdString>, pass_through<Loc>, pass_through<bool>,
+ pass_through<bool>>::def_wrap(ctx_cls, "addBel", "name"_a, "type"_a, "loc"_a, "gb"_a, "hidden"_a);
fn_wrapper_3a_v<Context, decltype(&Context::addBelInput), &Context::addBelInput, conv_from_str<IdStringList>,
conv_from_str<IdString>, conv_from_str<IdStringList>>::def_wrap(ctx_cls, "addBelInput", "bel"_a,
"name"_a, "wire"_a);
diff --git a/generic/examples/simple.py b/generic/examples/simple.py
index 9379b505..4b7f4025 100644
--- a/generic/examples/simple.py
+++ b/generic/examples/simple.py
@@ -20,13 +20,13 @@ for x in range(X):
if x == y:
continue
for z in range(2):
- ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False)
+ ctx.addBel(name="X%dY%d_IO%d" % (x, y, z), type="GENERIC_IOB", loc=Loc(x, y, z), gb=False, hidden=False)
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="I", wire="X%dY%dZ%d_I0" % (x, y, z))
ctx.addBelInput(bel="X%dY%d_IO%d" % (x, y, z), name="EN", wire="X%dY%dZ%d_I1" % (x, y, z))
ctx.addBelOutput(bel="X%dY%d_IO%d" % (x, y, z), name="O", wire="X%dY%dZ%d_Q" % (x, y, z))
else:
for z in range(N):
- ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False)
+ ctx.addBel(name="X%dY%d_SLICE%d" % (x, y, z), type="GENERIC_SLICE", loc=Loc(x, y, z), gb=False, hidden=False)
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="CLK", wire="X%dY%dZ%d_CLK" % (x, y, z))
for k in range(K):
ctx.addBelInput(bel="X%dY%d_SLICE%d" % (x, y, z), name="I[%d]" % k, wire="X%dY%dZ%d_I%d" % (x, y, z, k))
diff --git a/ice40/arch.h b/ice40/arch.h
index 5df072f9..30b5f871 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -849,7 +849,7 @@ struct Arch : BaseArch<ArchRanges>
// Assign architecture-specific arguments to nets and cells, which must be
// called between packing or further
// netlist modifications, and validity checks
- void assignArchInfo();
+ void assignArchInfo() override;
void assignCellInfo(CellInfo *cell);
// -------------------------------------------------
diff --git a/nexus/arch.h b/nexus/arch.h
index d81605af..963b5b2f 100644
--- a/nexus/arch.h
+++ b/nexus/arch.h
@@ -1118,7 +1118,7 @@ struct Arch : BaseArch<ArchRanges>
WireId getPipSrcWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).from_wire); }
- WireId getPipDstWire(PipId pip) const { return canonical_wire(pip.tile, pip_data(pip).to_wire); }
+ WireId getPipDstWire(PipId pip) const override { return canonical_wire(pip.tile, pip_data(pip).to_wire); }
DelayInfo getPipDelay(PipId pip) const override
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 04:14:32 +0000