diff options
| -rw-r--r-- | common/command.cc | 3 | ||||
| -rw-r--r-- | common/nextpnr.h | 2 | ||||
| -rw-r--r-- | common/sdf.cc | 21 | ||||
| -rw-r--r-- | ice40/cells.cc | 2 |
4 files changed, 20 insertions, 8 deletions
diff --git a/common/command.cc b/common/command.cc index f7f804a0..fd310789 100644 --- a/common/command.cc +++ b/common/command.cc @@ -150,6 +150,7 @@ po::options_description CommandHandler::getGeneralOptions() general.add_options()("timing-allow-fail", "allow timing to fail in design"); general.add_options()("no-tmdriv", "disable timing-driven placement"); general.add_options()("sdf", po::value<std::string>(), "SDF delay back-annotation file to write"); + general.add_options()("sdf-cvc", "enable tweaks for SDF file compatibility with the CVC simulator"); return general; } @@ -343,7 +344,7 @@ int CommandHandler::executeMain(std::unique_ptr<Context> ctx) std::ofstream f(filename); if (!f) log_error("Failed to open SDF file '%s' for writing.\n", filename.c_str()); - ctx->writeSDF(f); + ctx->writeSDF(f, vm.count("sdf-cvc")); } #ifndef NO_PYTHON diff --git a/common/nextpnr.h b/common/nextpnr.h index 89e9c4f0..24f6948b 100644 --- a/common/nextpnr.h +++ b/common/nextpnr.h @@ -809,7 +809,7 @@ struct Context : Arch, DeterministicRNG // -------------------------------------------------------------- // provided by sdf.cc - void writeSDF(std::ostream &out) const; + void writeSDF(std::ostream &out, bool cvc_mode = false) const; // -------------------------------------------------------------- diff --git a/common/sdf.cc b/common/sdf.cc index 769728e4..b9606907 100644 --- a/common/sdf.cc +++ b/common/sdf.cc @@ -78,6 +78,7 @@ struct Interconnect struct SDFWriter { + bool cvc_mode = false; std::vector<Cell> cells; std::vector<Interconnect> conn; std::string sdfversion, design, vendor, program; @@ -98,7 +99,7 @@ struct SDFWriter { std::string esc; for (char c : name) { - if (c == '$' || c == '\\' || c == '[' || c == ']' || c == ':') + if (c == '$' || c == '\\' || c == '[' || c == ']' || c == ':' || (cvc_mode && c == '.')) esc += '\\'; esc += c; } @@ -128,10 +129,19 @@ struct SDFWriter void write_delay(std::ostream &out, const MinMaxTyp &delay) { - out << "(" << delay.min << ":" << delay.typ << ":" << delay.max << ")"; + if (cvc_mode) + out << "(" << int(delay.min) << ":" << int(delay.typ) << ":" << int(delay.max) << ")"; + else + out << "(" << delay.min << ":" << delay.typ << ":" << delay.max << ")"; } - void write_port(std::ostream &out, const CellPort &port) { out << escape_name(port.cell + "/" + port.port); } + void write_port(std::ostream &out, const CellPort &port) + { + if (cvc_mode) + out << escape_name(port.cell) + "." + escape_name(port.port); + else + out << escape_name(port.cell + "/" + port.port); + } void write_portedge(std::ostream &out, const PortAndEdge &pe) { @@ -146,7 +156,7 @@ struct SDFWriter out << " (DESIGN " << format_name(design) << ")" << std::endl; out << " (VENDOR " << format_name(vendor) << ")" << std::endl; out << " (PROGRAM " << format_name(program) << ")" << std::endl; - out << " (DIVIDER /)" << std::endl; + out << " (DIVIDER " << (cvc_mode ? "." : "/") << ")" << std::endl; out << " (TIMESCALE 1ps)" << std::endl; // Write interconnect delays, with the main design begin a "cell" out << " (CELL" << std::endl; @@ -210,10 +220,11 @@ struct SDFWriter } // namespace SDF -void Context::writeSDF(std::ostream &out) const +void Context::writeSDF(std::ostream &out, bool cvc_mode) const { using namespace SDF; SDFWriter wr; + wr.cvc_mode = cvc_mode; wr.design = str_or_default(attrs, id("module"), "top"); wr.sdfversion = "3.0"; wr.vendor = "nextpnr"; diff --git a/ice40/cells.cc b/ice40/cells.cc index 3f1a0fbf..3def82bf 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -69,7 +69,7 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6); new_cell->params[ctx->id("PULLUP")] = Property::State::S0; new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0; - new_cell->params[ctx->id("IOSTANDARD")] = Property("SB_LVCMOS"); + new_cell->params[ctx->id("IO_STANDARD")] = Property("SB_LVCMOS"); add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT); |