diff options
Diffstat (limited to 'common/kernel/nextpnr_types.h')
-rw-r--r-- | common/kernel/nextpnr_types.h | 86 |
1 files changed, 59 insertions, 27 deletions
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h index c21182cc..e4042aec 100644 --- a/common/kernel/nextpnr_types.h +++ b/common/kernel/nextpnr_types.h @@ -160,6 +160,59 @@ struct PortInfo struct Context; +enum TimingPortClass +{ + TMG_CLOCK_INPUT, // Clock input to a sequential cell + TMG_GEN_CLOCK, // Generated clock output (PLL, DCC, etc) + TMG_REGISTER_INPUT, // Input to a register, with an associated clock (may also have comb. fanout too) + TMG_REGISTER_OUTPUT, // Output from a register + TMG_COMB_INPUT, // Combinational input, no paths end here + TMG_COMB_OUTPUT, // Combinational output, no paths start here + TMG_STARTPOINT, // Unclocked primary startpoint, such as an IO cell output + TMG_ENDPOINT, // Unclocked primary endpoint, such as an IO cell input + TMG_IGNORE, // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis +}; + +enum ClockEdge +{ + RISING_EDGE, + FALLING_EDGE +}; + +struct TimingClockingInfo +{ + IdString clock_port; // Port name of clock domain + ClockEdge edge; + DelayPair setup, hold; // Input timing checks + DelayQuad clockToQ; // Output clock-to-Q time +}; + +struct PseudoCell +{ + virtual Loc getLocation() const = 0; + virtual WireId getPortWire(IdString port) const = 0; + + virtual bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const = 0; + virtual TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const = 0; + virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const = 0; + virtual ~PseudoCell(){}; +}; + +struct RegionPlug : PseudoCell +{ + RegionPlug(Loc loc) : loc(loc){}; // 'loc' is a notional location for the placer only + Loc getLocation() const override { return loc; } + WireId getPortWire(IdString port) const override { return port_wires.at(port); } + + // TODO: partial reconfiguration region timing + bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; } + TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; } + virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; } + + dict<IdString, WireId> port_wires; + Loc loc; +}; + struct CellInfo : ArchCellInfo { CellInfo(Context *ctx, IdString name, IdString type) : ctx(ctx), name(name), type(type){}; @@ -179,6 +232,8 @@ struct CellInfo : ArchCellInfo Region *region = nullptr; + std::unique_ptr<PseudoCell> pseudo_cell{}; + void addInput(IdString name); void addOutput(IdString name); void addInout(IdString name); @@ -190,6 +245,10 @@ struct CellInfo : ArchCellInfo // check whether a bel complies with the cell's region constraint bool testRegion(BelId bel) const; + bool isPseudo() const { return bool(pseudo_cell); } + + Loc getLocation() const; + NetInfo *getPort(IdString name) { auto found = ports.find(name); @@ -212,33 +271,6 @@ struct CellInfo : ArchCellInfo int new_offset, bool new_brackets, int width); }; -enum TimingPortClass -{ - TMG_CLOCK_INPUT, // Clock input to a sequential cell - TMG_GEN_CLOCK, // Generated clock output (PLL, DCC, etc) - TMG_REGISTER_INPUT, // Input to a register, with an associated clock (may also have comb. fanout too) - TMG_REGISTER_OUTPUT, // Output from a register - TMG_COMB_INPUT, // Combinational input, no paths end here - TMG_COMB_OUTPUT, // Combinational output, no paths start here - TMG_STARTPOINT, // Unclocked primary startpoint, such as an IO cell output - TMG_ENDPOINT, // Unclocked primary endpoint, such as an IO cell input - TMG_IGNORE, // Asynchronous to all clocks, "don't care", and should be ignored (false path) for analysis -}; - -enum ClockEdge -{ - RISING_EDGE, - FALLING_EDGE -}; - -struct TimingClockingInfo -{ - IdString clock_port; // Port name of clock domain - ClockEdge edge; - DelayPair setup, hold; // Input timing checks - DelayQuad clockToQ; // Output clock-to-Q time -}; - struct ClockConstraint { DelayPair high; |