2 files changed, 7 insertions, 2 deletions
diff --git a/common/nextpnr.cc b/common/nextpnr.cc
index ab4601a6..d73c0c02 100644
--- a/common/nextpnr.cc
+++ b/common/nextpnr.cc
@@ -474,10 +474,10 @@ void BaseCtx::addClock(IdString net, float freq)
     cc->period = getCtx()->getDelayFromNS(1000 / freq);
     cc->high = getCtx()->getDelayFromNS(500 / freq);
     cc->low = getCtx()->getDelayFromNS(500 / freq);
-    if (!nets.count(net)) {
+    if (!net_aliases.count(net)) {
         log_warning("net '%s' does not exist in design, ignoring clock constraint\n", net.c_str(this));
     } else {
-        nets.at(net)->clkconstr = std::move(cc);
+        getNetByAlias(net)->clkconstr = std::move(cc);
         log_info("constraining clock net '%s' to %.02f MHz\n", net.c_str(this), freq);
     }
 }
diff --git a/common/nextpnr.h b/common/nextpnr.h
index 177048bf..4f9f7f23 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -609,6 +609,9 @@ struct BaseCtx
     std::unordered_map<IdString, std::unique_ptr<NetInfo>> nets;
     std::unordered_map<IdString, std::unique_ptr<CellInfo>> cells;
 
+    // Aliases for nets, which may have more than one name due to assignments and hierarchy
+    std::unordered_map<IdString, IdString> net_aliases;
+
     // Top-level ports
     std::unordered_map<IdString, PortInfo> ports;
 
@@ -738,6 +741,8 @@ struct BaseCtx
     TimingConstrObjectId timingCellObject(CellInfo *cell);
     TimingConstrObjectId timingPortObject(CellInfo *cell, IdString port);
 
+    NetInfo *getNetByAlias(IdString alias) const { return nets.at(net_aliases.at(alias)).get(); }
+
     void addConstraint(std::unique_ptr<TimingConstraint> constr);
     void removeConstraint(IdString constrName);