diff options
Diffstat (limited to 'cyclonev/arch.cc')
| -rw-r--r-- | cyclonev/arch.cc | 96 |
1 files changed, 95 insertions, 1 deletions
diff --git a/cyclonev/arch.cc b/cyclonev/arch.cc index ac19b7d2..c4b21b4a 100644 --- a/cyclonev/arch.cc +++ b/cyclonev/arch.cc @@ -106,6 +106,100 @@ void Arch::unbindBel(BelId bel) refreshUiBel(bel); } -bool Arch::checkBelAvail(BelId bel) const { return bels.at(bel).bound_cell == nullptr; } +std::vector<BelId> Arch::getBels() const +{ + // This should probably be redesigned, but it's a hack. + std::vector<BelId> bels{}; + + for (int x = 0; x < cyclonev->get_tile_sx(); x++) { + for (int y = 0; y < cyclonev->get_tile_sy(); y++) { + CycloneV::pos_t pos = cyclonev->xy2pos(x, y); + + for (CycloneV::block_type_t bel : cyclonev->pos_get_bels(pos)) { + switch (bel) { + case CycloneV::block_type_t::LAB: + /* + * nextpnr and mistral disagree on what a BEL is: mistral thinks an entire LAB + * is one BEL, but nextpnr wants something with more precision. + * + * One LAB contains 10 ALMs. + * One ALM contains 2 LUT outputs and 4 flop outputs. + */ + for (int z = 0; z < 60; z++) { + bels.push_back(BelId(pos, z)); + } + case CycloneV::block_type_t::GPIO: + // GPIO tiles contain 4 pins. + for (int z = 0; z < 4; z++) { + bels.push_back(BelId(pos, z)); + } + default: + continue; + } + } + } + } + + return bels; +} + +std::vector<BelId> Arch::getBelsByTile(int x, int y) const +{ + // This should probably be redesigned, but it's a hack. + std::vector<BelId> bels{}; + + CycloneV::pos_t pos = cyclonev->xy2pos(x, y); + + for (CycloneV::block_type_t bel : cyclonev->pos_get_bels(pos)) { + switch (bel) { + case CycloneV::block_type_t::LAB: + /* + * nextpnr and mistral disagree on what a BEL is: mistral thinks an entire LAB + * is one BEL, but nextpnr wants something with more precision. + * + * One LAB contains 10 ALMs. + * One ALM contains 2 LUT outputs and 4 flop outputs. + */ + for (int z = 0; z < 60; z++) { + bels.push_back(BelId(pos, z)); + } + case CycloneV::block_type_t::GPIO: + // GPIO tiles contain 4 pins. + for (int z = 0; z < 4; z++) { + bels.push_back(BelId(pos, z)); + } + default: + continue; + } + } + + return bels; +} + +IdString Arch::getBelType(BelId bel) const +{ + CycloneV::pos_t pos = cyclonev->xy2pos(x, y); + + for (CycloneV::block_type_t bel : cyclonev->pos_get_bels(pos)) { + switch (bel) { + case CycloneV::block_type_t::LAB: + /* + * nextpnr and mistral disagree on what a BEL is: mistral thinks an entire LAB + * is one BEL, but nextpnr wants something with more precision. + * + * One LAB contains 10 ALMs. + * One ALM contains 2 LUT outputs and 4 flop outputs. + */ + return IdString(this, "LAB"); + case CycloneV::block_type_t::GPIO: + // GPIO tiles contain 4 pins. + return IdString(this, "GPIO"); + default: + continue; + } + } + + return IdString(); +} NEXTPNR_NAMESPACE_END
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