2 files changed, 25 insertions, 0 deletions
diff --git a/dummy/arch.cc b/dummy/arch.cc
index 58298c4e..103eee4d 100644
--- a/dummy/arch.cc
+++ b/dummy/arch.cc
@@ -176,4 +176,22 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const
     return ret;
 }
 
+// ---------------------------------------------------------------
+
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort,
+                        IdString toPort, delay_t &delay) const
+{
+    return false;
+}
+
+IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
+{
+    return IdString();
+}
+
+bool Arch::isClockPort(const CellInfo *cell, IdString port) const
+{
+    return false;
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/dummy/arch.h b/dummy/arch.h
index 925c231f..43ab3290 100644
--- a/dummy/arch.h
+++ b/dummy/arch.h
@@ -32,7 +32,9 @@ struct DelayInfo
     delay_t delay = 0;
 
     delay_t raiseDelay() const { return delay; }
+
     delay_t fallDelay() const { return delay; }
+
     delay_t avgDelay() const { return delay; }
 
     DelayInfo operator+(const DelayInfo &other) const
@@ -133,6 +135,11 @@ struct Arch : BaseCtx
     std::unordered_set<BelId> belGraphicsReload;
     std::unordered_set<WireId> wireGraphicsReload;
     std::unordered_set<PipId> pipGraphicsReload;
+
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort,
+                      delay_t &delay) const;
+    IdString getPortClock(const CellInfo *cell, IdString port) const;
+    bool isClockPort(const CellInfo *cell, IdString port) const;
 };
 
 NEXTPNR_NAMESPACE_END