diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch_pybindings.cc | 3 | ||||
| -rw-r--r-- | ecp5/bitstream.cc | 4 | ||||
| -rw-r--r-- | ecp5/gfx.cc | 4 | ||||
| -rw-r--r-- | ecp5/pack.cc | 6 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 2 |
5 files changed, 9 insertions, 10 deletions
diff --git a/ecp5/arch_pybindings.cc b/ecp5/arch_pybindings.cc index cd5e31c3..951745af 100644 --- a/ecp5/arch_pybindings.cc +++ b/ecp5/arch_pybindings.cc @@ -46,6 +46,9 @@ void arch_wrap_python() .def("place", &Context::place) .def("route", &Context::route); + fn_wrapper_2a<Context, decltype(&Context::isValidBelForCell), &Context::isValidBelForCell, pass_through<bool>, + addr_and_unwrap<CellInfo>, conv_from_str<BelId>>::def_wrap(ctx_cls, "isValidBelForCell"); + typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap; typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap; typedef std::unordered_map<IdString, IdString> AliasMap; diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index 207ba048..bc8a6c55 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -178,7 +178,7 @@ static std::string get_pio_tile(Context *ctx, BelId bel) { static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"}; static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"}; - static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set<std::string> pioa_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"}; static const std::set<std::string> piob_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); @@ -215,7 +215,7 @@ static std::string get_pic_tile(Context *ctx, BelId bel) static const std::set<std::string> picab_r = {"PICR0", "PICR0_DQS2"}; static const std::set<std::string> piccd_r = {"PICR2", "PICR2_DQS1", "MIB_CIB_LR_A"}; - static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0"}; + static const std::set<std::string> pica_b = {"PICB0", "EFB0_PICB0", "EFB2_PICB0", "SPICB0"}; static const std::set<std::string> picb_b = {"PICB1", "EFB1_PICB1", "EFB3_PICB1"}; std::string pio_name = ctx->locInfo(bel)->bel_data[bel.index].name.get(); diff --git a/ecp5/gfx.cc b/ecp5/gfx.cc index dc6bed21..da96b76d 100644 --- a/ecp5/gfx.cc +++ b/ecp5/gfx.cc @@ -32,14 +32,10 @@ const float slice_pitch = 0.0374 + 0.0068; const float io_cell_v_x1 = 0.76; const float io_cell_v_x2 = 0.95; const float io_cell_v_y1 = 0.05; -const float io_cell_v_y2 = 0.15; -const float io_cell_v_pitch = 0.125; const float io_cell_gap = 0.10; const float io_cell_h_x1 = 0.05; -const float io_cell_h_x2 = 0.14; const float io_cell_h_y1 = 0.05; const float io_cell_h_y2 = 0.24; -const float io_cell_h_pitch = 0.125; const float wire_distance = 0.0017f; const float wire_distance_small = 0.00085f; diff --git a/ecp5/pack.cc b/ecp5/pack.cc index 3867ab3d..f5e8a544 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -2185,15 +2185,15 @@ class Ecp5Packer if (ci->ports.count(id_LOADN)) replace_port(ci, id_LOADN, iol, id_LOADN); else - tie_zero(ci, id_LOADN); + tie_zero(iol, id_LOADN); if (ci->ports.count(id_MOVE)) replace_port(ci, id_MOVE, iol, id_MOVE); else - tie_zero(ci, id_MOVE); + tie_zero(iol, id_MOVE); if (ci->ports.count(id_DIRECTION)) replace_port(ci, id_DIRECTION, iol, id_DIRECTION); else - tie_zero(ci, id_DIRECTION); + tie_zero(iol, id_DIRECTION); if (ci->ports.count(id_CFLAG)) replace_port(ci, id_CFLAG, iol, id_CFLAG); } diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index c8589b6c..a21c4b3d 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -521,7 +521,7 @@ def write_database(dev_name, chip, ddrg, endianness): loc, bel_idx, bank, func, dqs = pin write_loc(loc, "abs_loc") bba.u32(bel_idx, "bel_index") - if func is not None: + if func is not None and func != "WRITEN": bba.s(func, "function_name") else: bba.r(None, "function_name") |