diff options
Diffstat (limited to 'ecp5')
| -rw-r--r-- | ecp5/arch.cc | 4 | ||||
| -rw-r--r-- | ecp5/arch.h | 3 | ||||
| -rw-r--r-- | ecp5/main.cc | 6 |
3 files changed, 10 insertions, 3 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 88b5e4d4..fa36e1f8 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -418,6 +418,8 @@ delay_t Arch::predictDelay(WireId src, WireId dst) const return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y)); } +delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; } + // ----------------------------------------------------------------------- bool Arch::place() { return placer1(getCtx()); } @@ -445,7 +447,7 @@ DecalXY Arch::getGroupDecal(GroupId pip) const { return {}; }; // ----------------------------------------------------------------------- -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { return false; } diff --git a/ecp5/arch.h b/ecp5/arch.h index 13f2db1f..5e181d49 100644 --- a/ecp5/arch.h +++ b/ecp5/arch.h @@ -781,6 +781,7 @@ struct Arch : BaseCtx delay_t getRipupDelayPenalty() const { return 200; } float getDelayNS(delay_t v) const { return v * 0.001; } uint32_t getDelayChecksum(delay_t v) const { return v; } + delay_t getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const; // ------------------------------------------------- @@ -802,7 +803,7 @@ struct Arch : BaseCtx // Get the delay through a cell from one port to another, returning false // if no path exists - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, delay_t &delay) const; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const; // Get the associated clock to a port, or empty if the port is combinational IdString getPortClock(const CellInfo *cell, IdString port) const; // Return true if a port is a clock diff --git a/ecp5/main.cc b/ecp5/main.cc index f2db74d7..9f683a7b 100644 --- a/ecp5/main.cc +++ b/ecp5/main.cc @@ -167,8 +167,12 @@ int main(int argc, char *argv[]) if (!ctx->pack() && !ctx->force) log_error("Packing design failed.\n"); - if (vm.count("freq")) + if (vm.count("freq")) { ctx->target_freq = vm["freq"].as<double>() * 1e6; + ctx->user_freq = true; + } else { + log_warning("Target frequency not specified. Will optimise for max frequency.\n"); + } assign_budget(ctx.get()); ctx->check(); print_utilisation(ctx.get()); |