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-rw-r--r--ecp5/arch.h26
-rw-r--r--ecp5/bitstream.cc4
-rw-r--r--ecp5/cells.cc2
-rw-r--r--ecp5/cells.h2
-rw-r--r--ecp5/globals.cc14
-rw-r--r--ecp5/lpf.cc5
-rw-r--r--ecp5/pack.cc29
7 files changed, 33 insertions, 49 deletions
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 063a3df6..be1a44d8 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -419,23 +419,9 @@ struct DelayKey
{
return celltype == other.celltype && from == other.from && to == other.to;
}
+ unsigned int hash() const { return mkhash(celltype.hash(), mkhash(from.hash(), to.hash())); }
};
-NEXTPNR_NAMESPACE_END
-namespace std {
-template <> struct hash<NEXTPNR_NAMESPACE_PREFIX DelayKey>
-{
- std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX DelayKey &dk) const noexcept
- {
- std::size_t seed = std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.celltype);
- seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.from) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
- seed ^= std::hash<NEXTPNR_NAMESPACE_PREFIX IdString>()(dk.to) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
- return seed;
- }
-};
-} // namespace std
-NEXTPNR_NAMESPACE_BEGIN
-
struct ArchRanges : BaseArchRanges
{
using ArchArgsT = ArchArgs;
@@ -458,15 +444,15 @@ struct Arch : BaseArch<ArchRanges>
const PackageInfoPOD *package_info;
const SpeedGradePOD *speed_grade;
- mutable std::unordered_map<IdStringList, PipId> pip_by_name;
+ mutable dict<IdStringList, PipId> pip_by_name;
std::vector<CellInfo *> bel_to_cell;
- std::unordered_map<WireId, int> wire_fanout;
+ dict<WireId, int> wire_fanout;
// fast access to X and Y IdStrings for building object names
std::vector<IdString> x_ids, y_ids;
// inverse of the above for name->object mapping
- std::unordered_map<IdString, int> id_to_x, id_to_y;
+ dict<IdString, int> id_to_x, id_to_y;
ArchArgs args;
Arch(ArchArgs args);
@@ -914,10 +900,10 @@ struct Arch : BaseArch<ArchRanges>
// Improves directivity of routing to DSP inputs, avoids issues
// with different routes to the same physical reset wire causing
// conflicts and slow routing
- std::unordered_map<WireId, std::pair<int, int>> wire_loc_overrides;
+ dict<WireId, std::pair<int, int>> wire_loc_overrides;
void setup_wire_locations();
- mutable std::unordered_map<DelayKey, std::pair<bool, DelayQuad>> celldelay_cache;
+ mutable dict<DelayKey, std::pair<bool, DelayQuad>> celldelay_cache;
static const std::string defaultPlacer;
static const std::vector<std::string> availablePlacers;
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index c8349f88..ac9d4a4d 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -669,8 +669,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
}
// Find bank voltages
- std::unordered_map<int, IOVoltage> bankVcc;
- std::unordered_map<int, bool> bankLvds, bankVref, bankDiff;
+ dict<int, IOVoltage> bankVcc;
+ dict<int, bool> bankLvds, bankVref, bankDiff;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 7f9f1579..edc80329 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -422,7 +422,7 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
}
void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
- std::unordered_set<IdString> &todelete_cells)
+ pool<IdString> &todelete_cells)
{
if (nxio->type == ctx->id("$nextpnr_ibuf")) {
trio->params[ctx->id("DIR")] = std::string("INPUT");
diff --git a/ecp5/cells.h b/ecp5/cells.h
index e66f8f21..20ba97b4 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -65,7 +65,7 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
// Convert a nextpnr IO buffer to a TRELLIS_IO
void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
- std::unordered_set<IdString> &todelete_cells);
+ pool<IdString> &todelete_cells);
NEXTPNR_NAMESPACE_END
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index 1e86fe6b..b840ac91 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -72,7 +72,7 @@ class Ecp5GlobalRouter
std::vector<NetInfo *> get_clocks()
{
- std::unordered_map<IdString, int> clockCount;
+ dict<IdString, int> clockCount;
for (auto &net : ctx->nets) {
NetInfo *ni = net.second.get();
if (ni->name == ctx->id("$PACKER_GND_NET") || ni->name == ctx->id("$PACKER_VCC_NET"))
@@ -147,7 +147,7 @@ class Ecp5GlobalRouter
WireId globalWire;
IdString global_name = ctx->id(fmt_str("G_HPBX" << std::setw(2) << std::setfill('0') << global_index << "00"));
std::queue<WireId> upstream;
- std::unordered_map<WireId, PipId> backtrace;
+ dict<WireId, PipId> backtrace;
upstream.push(userWire);
bool already_routed = false;
WireId next;
@@ -230,7 +230,7 @@ class Ecp5GlobalRouter
bool simple_router(NetInfo *net, WireId src, WireId dst, bool allow_fail = false)
{
std::queue<WireId> visit;
- std::unordered_map<WireId, PipId> backtrace;
+ dict<WireId, PipId> backtrace;
visit.push(src);
WireId cursor;
while (true) {
@@ -340,7 +340,7 @@ class Ecp5GlobalRouter
bool has_short_route(WireId src, WireId dst, int thresh = 7)
{
std::queue<WireId> visit;
- std::unordered_map<WireId, PipId> backtrace;
+ dict<WireId, PipId> backtrace;
visit.push(src);
WireId cursor;
while (true) {
@@ -376,7 +376,7 @@ class Ecp5GlobalRouter
return length < thresh;
}
- std::unordered_set<WireId> used_pclkcib;
+ pool<WireId> used_pclkcib;
std::set<WireId> get_candidate_pclkcibs(BelId dcc)
{
@@ -535,7 +535,7 @@ class Ecp5GlobalRouter
fab_globals.insert(i);
}
std::vector<std::pair<PortRef *, int>> toroute;
- std::unordered_map<int, NetInfo *> clocks;
+ dict<int, NetInfo *> clocks;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_DCCA) {
@@ -595,7 +595,7 @@ class Ecp5GlobalRouter
WireId src = ctx->getNetinfoSourceWire(ni);
WireId dst = ctx->getBelPinWire(ci->bel, pin);
std::queue<WireId> visit;
- std::unordered_map<WireId, PipId> backtrace;
+ dict<WireId, PipId> backtrace;
visit.push(dst);
int iter = 0;
WireId cursor;
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 6d134e8d..39576fcb 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -19,7 +19,6 @@
#include <boost/algorithm/string.hpp>
#include <sstream>
-#include <unordered_set>
#include "arch.h"
#include "log.h"
@@ -27,7 +26,7 @@
NEXTPNR_NAMESPACE_BEGIN
-static const std::unordered_set<std::string> sysconfig_keys = {
+static const pool<std::string> sysconfig_keys = {
"SLAVE_SPI_PORT", "MASTER_SPI_PORT", "SLAVE_PARALLEL_PORT",
"BACKGROUND_RECONFIG", "DONE_EX", "DONE_OD",
"DONE_PULL", "MCCLK_FREQ", "TRANSFR",
@@ -35,7 +34,7 @@ static const std::unordered_set<std::string> sysconfig_keys = {
"COMPRESS_CONFIG", "CONFIG_MODE", "INBUF",
};
-static const std::unordered_set<std::string> iobuf_keys = {
+static const pool<std::string> iobuf_keys = {
"IO_TYPE", "BANK", "BANK_VCC", "VREF", "PULLMODE", "DRIVE", "SLEWRATE",
"CLAMP", "OPENDRAIN", "DIFFRESISTOR", "DIFFDRIVE", "HYSTERESIS", "TERMINATION",
};
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index db5d22a1..19eda9e2 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -21,7 +21,6 @@
#include <boost/optional.hpp>
#include <iterator>
#include <queue>
-#include <unordered_set>
#include "cells.h"
#include "chain_utils.h"
#include "design_utils.h"
@@ -261,7 +260,7 @@ class Ecp5Packer
void pair_luts()
{
log_info("Finding LUT-LUT pairs...\n");
- std::unordered_set<IdString> procdLuts;
+ pool<IdString> procdLuts;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
@@ -1134,7 +1133,7 @@ class Ecp5Packer
// Used for packing an FF into a nearby SLICE
template <typename TFunc> CellInfo *find_nearby_cell(CellInfo *origin, TFunc Func)
{
- std::unordered_set<CellInfo *> visited_cells;
+ pool<CellInfo *, hash_ptr_ops> visited_cells;
std::queue<CellInfo *> to_visit;
visited_cells.insert(origin);
to_visit.push(origin);
@@ -1971,7 +1970,7 @@ class Ecp5Packer
IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk));
std::queue<WireId> upstream;
- std::unordered_map<WireId, PipId> backtrace;
+ dict<WireId, PipId> backtrace;
upstream.push(userWire);
WireId next;
while (true) {
@@ -2026,7 +2025,7 @@ class Ecp5Packer
new_cells.push_back(std::move(zero_cell));
}
- std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg;
+ dict<IdString, std::pair<bool, int>> dqsbuf_dqsg;
// Pack DQSBUFs
void pack_dqsbuf()
{
@@ -2119,7 +2118,7 @@ class Ecp5Packer
// Pack IOLOGIC
void pack_iologic()
{
- std::unordered_map<IdString, CellInfo *> pio_iologic;
+ dict<IdString, CellInfo *> pio_iologic;
auto set_iologic_sclk = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input, bool disconnect = true) {
NetInfo *sclk = nullptr;
@@ -2779,7 +2778,7 @@ class Ecp5Packer
}
}
flush_cells();
- std::unordered_set<BelId> used_eclksyncb;
+ pool<BelId> used_eclksyncb;
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_CLKDIVF) {
@@ -2967,7 +2966,7 @@ class Ecp5Packer
auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
- std::unordered_set<IdString> user_constrained, changed_nets;
+ pool<IdString> user_constrained, changed_nets;
for (auto &net : ctx->nets) {
if (net.second->clkconstr != nullptr)
user_constrained.insert(net.first);
@@ -3041,7 +3040,7 @@ class Ecp5Packer
const int itermax = 5000;
while (!changed_nets.empty() && iter < itermax) {
++iter;
- std::unordered_set<IdString> changed_cells;
+ pool<IdString> changed_cells;
for (auto net : changed_nets) {
for (auto &user : ctx->nets.at(net)->users)
if (user.port == id_CLKI || user.port == id_ECLKI || user.port == id_CLK0 || user.port == id_CLK1)
@@ -3051,7 +3050,7 @@ class Ecp5Packer
changed_cells.insert(drv.cell->name);
}
changed_nets.clear();
- for (auto cell : sorted(changed_cells)) {
+ for (auto cell : changed_cells) {
CellInfo *ci = ctx->cells.at(cell).get();
if (ci->type == id_CLKDIVF) {
std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
@@ -3152,7 +3151,7 @@ class Ecp5Packer
private:
Context *ctx;
- std::unordered_set<IdString> packed_cells;
+ pool<IdString> packed_cells;
std::vector<std::unique_ptr<CellInfo>> new_cells;
struct SliceUsage
@@ -3163,10 +3162,10 @@ class Ecp5Packer
bool mux5_used = false, muxx_used = false;
};
- std::unordered_map<IdString, SliceUsage> sliceUsage;
- std::unordered_map<IdString, IdString> lutffPairs;
- std::unordered_map<IdString, IdString> fflutPairs;
- std::unordered_map<IdString, IdString> lutPairs;
+ dict<IdString, SliceUsage> sliceUsage;
+ dict<IdString, IdString> lutffPairs;
+ dict<IdString, IdString> fflutPairs;
+ dict<IdString, IdString> lutPairs;
};
// Main pack function
bool Arch::pack()
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 04:27:10 +0000