diff options
Diffstat (limited to 'fpga_interchange/examples/archcheck')
| -rw-r--r-- | fpga_interchange/examples/archcheck/Makefile | 16 | ||||
| -rw-r--r-- | fpga_interchange/examples/archcheck/test_data.yaml | 7 |
2 files changed, 23 insertions, 0 deletions
diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile new file mode 100644 index 00000000..cf82013b --- /dev/null +++ b/fpga_interchange/examples/archcheck/Makefile @@ -0,0 +1,16 @@ +include ../common.mk + +PACKAGE := csg324 + +.PHONY: check check_test_data + +check: check_test_data + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --package $(PACKAGE) \ + --test + +check_test_data: + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --run $(NEXTPNR_PATH)/python/check_arch_api.py diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml new file mode 100644 index 00000000..b41112cf --- /dev/null +++ b/fpga_interchange/examples/archcheck/test_data.yaml @@ -0,0 +1,7 @@ +pip_test: + - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 + dst_wire: SLICE_X15Y93.SLICEL/D3 +bel_pin_test: + - bel: SLICE_X15Y93.SLICEL/D6LUT + pin: A3 + wire: SLICE_X15Y93.SLICEL/D3 |