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| author | gatecat <gatecat@ds0.me> | 2021-02-19 08:41:58 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-19 08:41:58 +0000 |
| commit | 5dcb59b13decab276ac736b0b06b4ccebcf83f62 (patch) | |
| tree | 67017806da1d36a6ec13fc538390b875b30309ab /fpga_interchange/examples/archcheck | |
| parent | b4a97efe4da95084ba5585c48d20681f68742fd4 (diff) | |
| parent | c21e23b3eb6fee48c2b2da384b2dd0cd2d4ad91f (diff) | |
| download | nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.gz nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.tar.bz2 nextpnr-5dcb59b13decab276ac736b0b06b4ccebcf83f62.zip | |
Merge pull request #576 from litghost/add_cell_bel_pin_mapping
Complete FPGA interchange Arch to the point where it can route a wire
Diffstat (limited to 'fpga_interchange/examples/archcheck')
| -rw-r--r-- | fpga_interchange/examples/archcheck/Makefile | 16 | ||||
| -rw-r--r-- | fpga_interchange/examples/archcheck/test_data.yaml | 7 |
2 files changed, 23 insertions, 0 deletions
diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile new file mode 100644 index 00000000..cf82013b --- /dev/null +++ b/fpga_interchange/examples/archcheck/Makefile @@ -0,0 +1,16 @@ +include ../common.mk + +PACKAGE := csg324 + +.PHONY: check check_test_data + +check: check_test_data + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --package $(PACKAGE) \ + --test + +check_test_data: + $(NEXTPNR_BIN) \ + --chipdb $(BBA_PATH) \ + --run $(NEXTPNR_PATH)/python/check_arch_api.py diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml new file mode 100644 index 00000000..b41112cf --- /dev/null +++ b/fpga_interchange/examples/archcheck/test_data.yaml @@ -0,0 +1,7 @@ +pip_test: + - src_wire: CLBLM_R_X11Y93/CLBLM_L_D3 + dst_wire: SLICE_X15Y93.SLICEL/D3 +bel_pin_test: + - bel: SLICE_X15Y93.SLICEL/D6LUT + pin: A3 + wire: SLICE_X15Y93.SLICEL/D3 |