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-rw-r--r--fpga_interchange/examples/lut/run.tcl14
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl
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+++ b/fpga_interchange/examples/lut/run.tcl
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+yosys -import
+
+read_verilog lut.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/lut.json