4 files changed, 0 insertions, 34 deletions
diff --git a/fpga_interchange/examples/lut/Makefile b/fpga_interchange/examples/lut/Makefile
deleted file mode 100644
index 54fc8994..00000000
--- a/fpga_interchange/examples/lut/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-DESIGN := lut
-DESIGN_TOP := top
-PACKAGE := csg324
-
-include ../template.mk
-
-build/lut.json: lut.v | build
-	yosys -c run.tcl
diff --git a/fpga_interchange/examples/lut/lut.v b/fpga_interchange/examples/lut/lut.v
deleted file mode 100644
index ca18e665..00000000
--- a/fpga_interchange/examples/lut/lut.v
+++ /dev/null
@@ -1,5 +0,0 @@
-module top(input i0, input i1, output o);
-
-assign o = i0 | i1;
-
-endmodule
diff --git a/fpga_interchange/examples/lut/lut.xdc b/fpga_interchange/examples/lut/lut.xdc
deleted file mode 100644
index 4f390f25..00000000
--- a/fpga_interchange/examples/lut/lut.xdc
+++ /dev/null
@@ -1,7 +0,0 @@
-set_property PACKAGE_PIN N16 [get_ports i0]
-set_property PACKAGE_PIN N15 [get_ports i1]
-set_property PACKAGE_PIN M17 [get_ports o]
-
-set_property IOSTANDARD LVCMOS33 [get_ports i0]
-set_property IOSTANDARD LVCMOS33 [get_ports i1]
-set_property IOSTANDARD LVCMOS33 [get_ports o]
diff --git a/fpga_interchange/examples/lut/run.tcl b/fpga_interchange/examples/lut/run.tcl
deleted file mode 100644
index 1edd8bb7..00000000
--- a/fpga_interchange/examples/lut/run.tcl
+++ /dev/null
@@ -1,14 +0,0 @@
-yosys -import
-
-read_verilog lut.v
-
-synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
-
-# opt_expr -undriven makes sure all nets are driven, if only by the $undef
-# net.
-opt_expr -undriven
-opt_clean
-
-setundef -zero -params
-
-write_json build/lut.json