5 files changed, 62 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/ff/CMakeLists.txt b/fpga_interchange/examples/tests/ff/CMakeLists.txt
new file mode 100644
index 00000000..ccf16d44
--- /dev/null
+++ b/fpga_interchange/examples/tests/ff/CMakeLists.txt
@@ -0,0 +1,19 @@
+add_interchange_test(
+    name ff_basys3
+    family ${family}
+    device xc7a35t
+    package cpg236
+    tcl run.tcl
+    xdc ff_basys3.xdc
+    sources ff.v
+)
+
+add_interchange_test(
+    name ff_arty
+    family ${family}
+    device xc7a35t
+    package csg324
+    tcl run.tcl
+    xdc ff_arty.xdc
+    sources ff.v
+)
diff --git a/fpga_interchange/examples/tests/ff/ff.v b/fpga_interchange/examples/tests/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/tests/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+    if(r)
+        q <= 1'b0;
+    else
+        q <= d;
+end
+
+endmodule
diff --git a/fpga_interchange/examples/tests/ff/ff_arty.xdc b/fpga_interchange/examples/tests/ff/ff_arty.xdc
new file mode 100644
index 00000000..3c132f1d
--- /dev/null
+++ b/fpga_interchange/examples/tests/ff/ff_arty.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property PACKAGE_PIN N15 [get_ports d]
+set_property PACKAGE_PIN N16 [get_ports r]
+set_property PACKAGE_PIN M17 [get_ports q]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports d]
+set_property IOSTANDARD LVCMOS33 [get_ports r]
+set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/tests/ff/ff_basys3.xdc b/fpga_interchange/examples/tests/ff/ff_basys3.xdc
new file mode 100644
index 00000000..ef65112a
--- /dev/null
+++ b/fpga_interchange/examples/tests/ff/ff_basys3.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN W5 [get_ports clk]
+set_property PACKAGE_PIN U16 [get_ports d]
+set_property PACKAGE_PIN E19 [get_ports r]
+set_property PACKAGE_PIN U19 [get_ports q]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports d]
+set_property IOSTANDARD LVCMOS33 [get_ports r]
+set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/tests/ff/run.tcl b/fpga_interchange/examples/tests/ff/run.tcl
new file mode 100644
index 00000000..b8d0df72
--- /dev/null
+++ b/fpga_interchange/examples/tests/ff/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog $::env(SOURCES)
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json $::env(OUT_JSON)