diff options
Diffstat (limited to 'fpga_interchange/examples/tests')
21 files changed, 257 insertions, 0 deletions
diff --git a/fpga_interchange/examples/tests/CMakeLists.txt b/fpga_interchange/examples/tests/CMakeLists.txt new file mode 100644 index 00000000..49b5b587 --- /dev/null +++ b/fpga_interchange/examples/tests/CMakeLists.txt @@ -0,0 +1,5 @@ +add_subdirectory(wire) +add_subdirectory(const_wire) +add_subdirectory(counter) +add_subdirectory(ff) +add_subdirectory(lut) diff --git a/fpga_interchange/examples/tests/const_wire/CMakeLists.txt b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt new file mode 100644 index 00000000..163f4a97 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name const_wire_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc wire.xdc + sources wire.v +) + +add_interchange_test( + name const_wire_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc wire.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/const_wire/run.tcl b/fpga_interchange/examples/tests/const_wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/const_wire/wire.v b/fpga_interchange/examples/tests/const_wire/wire.v new file mode 100644 index 00000000..5b1ab692 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.v @@ -0,0 +1,8 @@ +module top(output o, output o2, output o3, output o4); + +assign o = 1'b0; +assign o2 = 1'b1; +assign o3 = 1'b0; +assign o4 = 1'b1; + +endmodule diff --git a/fpga_interchange/examples/tests/const_wire/wire.xdc b/fpga_interchange/examples/tests/const_wire/wire.xdc new file mode 100644 index 00000000..0d96fc45 --- /dev/null +++ b/fpga_interchange/examples/tests/const_wire/wire.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN N15 [get_ports o] +set_property PACKAGE_PIN N16 [get_ports o2] +set_property PACKAGE_PIN P17 [get_ports o3] +set_property PACKAGE_PIN R17 [get_ports o4] + +set_property IOSTANDARD LVCMOS33 [get_ports o] +set_property IOSTANDARD LVCMOS33 [get_ports o2] +set_property IOSTANDARD LVCMOS33 [get_ports o3] +set_property IOSTANDARD LVCMOS33 [get_ports o4] diff --git a/fpga_interchange/examples/tests/counter/CMakeLists.txt b/fpga_interchange/examples/tests/counter/CMakeLists.txt new file mode 100644 index 00000000..e105a86a --- /dev/null +++ b/fpga_interchange/examples/tests/counter/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name counter_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc counter.xdc + sources counter.v +) + +add_interchange_test( + name counter_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc counter.xdc + sources counter.v +) diff --git a/fpga_interchange/examples/tests/counter/counter.v b/fpga_interchange/examples/tests/counter/counter.v new file mode 100644 index 00000000..00f52a20 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter.v @@ -0,0 +1,15 @@ +module top(input clk, input rst, output [7:4] io_led); + +reg [31:0] counter = 32'b0; + +assign io_led = counter >> 22; + +always @(posedge clk) +begin + if(rst) + counter <= 32'b0; + else + counter <= counter + 1; +end + +endmodule diff --git a/fpga_interchange/examples/tests/counter/counter.xdc b/fpga_interchange/examples/tests/counter/counter.xdc new file mode 100644 index 00000000..7cbe67f6 --- /dev/null +++ b/fpga_interchange/examples/tests/counter/counter.xdc @@ -0,0 +1,22 @@ +## basys3 breakout board +set_property PACKAGE_PIN W5 [get_ports clk] +set_property PACKAGE_PIN V17 [get_ports rst] +#set_property PACKAGE_PIN U16 [get_ports io_led[0]] +#set_property PACKAGE_PIN E19 [get_ports io_led[1]] +#set_property PACKAGE_PIN U19 [get_ports io_led[2]] +#set_property PACKAGE_PIN V19 [get_ports io_led[3]] +set_property PACKAGE_PIN U16 [get_ports io_led[4]] +set_property PACKAGE_PIN E19 [get_ports io_led[5]] +set_property PACKAGE_PIN U19 [get_ports io_led[6]] +set_property PACKAGE_PIN V19 [get_ports io_led[7]] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports rst] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]] +set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[0]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[1]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[2]] +#set_property IOSTANDARD LVCMOS33 [get_ports io_led[3]] diff --git a/fpga_interchange/examples/tests/counter/run.tcl b/fpga_interchange/examples/tests/counter/run.tcl new file mode 100644 index 00000000..7cd9f10f --- /dev/null +++ b/fpga_interchange/examples/tests/counter/run.tcl @@ -0,0 +1,15 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp +techmap -map ../remap.v + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/ff/CMakeLists.txt b/fpga_interchange/examples/tests/ff/CMakeLists.txt new file mode 100644 index 00000000..66074c64 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name ff_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc ff.xdc + sources ff.v +) + +add_interchange_test( + name ff_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc ff.xdc + sources ff.v +) diff --git a/fpga_interchange/examples/tests/ff/ff.v b/fpga_interchange/examples/tests/ff/ff.v new file mode 100644 index 00000000..1c271042 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/ff.v @@ -0,0 +1,11 @@ +module top(input clk, input d, input r, output reg q); + +always @(posedge clk) +begin + if(r) + q <= 1'b0; + else + q <= d; +end + +endmodule diff --git a/fpga_interchange/examples/tests/ff/ff.xdc b/fpga_interchange/examples/tests/ff/ff.xdc new file mode 100644 index 00000000..3c132f1d --- /dev/null +++ b/fpga_interchange/examples/tests/ff/ff.xdc @@ -0,0 +1,9 @@ +set_property PACKAGE_PIN P17 [get_ports clk] +set_property PACKAGE_PIN N15 [get_ports d] +set_property PACKAGE_PIN N16 [get_ports r] +set_property PACKAGE_PIN M17 [get_ports q] + +set_property IOSTANDARD LVCMOS33 [get_ports clk] +set_property IOSTANDARD LVCMOS33 [get_ports d] +set_property IOSTANDARD LVCMOS33 [get_ports r] +set_property IOSTANDARD LVCMOS33 [get_ports q] diff --git a/fpga_interchange/examples/tests/ff/run.tcl b/fpga_interchange/examples/tests/ff/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/ff/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/lut/CMakeLists.txt b/fpga_interchange/examples/tests/lut/CMakeLists.txt new file mode 100644 index 00000000..4ec74b3d --- /dev/null +++ b/fpga_interchange/examples/tests/lut/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name lut_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc lut.xdc + sources lut.v +) + +add_interchange_test( + name lut_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc lut.xdc + sources lut.v +) diff --git a/fpga_interchange/examples/tests/lut/lut.v b/fpga_interchange/examples/tests/lut/lut.v new file mode 100644 index 00000000..ca18e665 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/lut.v @@ -0,0 +1,5 @@ +module top(input i0, input i1, output o); + +assign o = i0 | i1; + +endmodule diff --git a/fpga_interchange/examples/tests/lut/lut.xdc b/fpga_interchange/examples/tests/lut/lut.xdc new file mode 100644 index 00000000..4f390f25 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/lut.xdc @@ -0,0 +1,7 @@ +set_property PACKAGE_PIN N16 [get_ports i0] +set_property PACKAGE_PIN N15 [get_ports i1] +set_property PACKAGE_PIN M17 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i0] +set_property IOSTANDARD LVCMOS33 [get_ports i1] +set_property IOSTANDARD LVCMOS33 [get_ports o] diff --git a/fpga_interchange/examples/tests/lut/run.tcl b/fpga_interchange/examples/tests/lut/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/lut/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/wire/CMakeLists.txt b/fpga_interchange/examples/tests/wire/CMakeLists.txt new file mode 100644 index 00000000..7736877f --- /dev/null +++ b/fpga_interchange/examples/tests/wire/CMakeLists.txt @@ -0,0 +1,17 @@ +add_interchange_test( + name wire_basys3 + part xc7a35tcpg236-1 + package cpg236 + tcl run.tcl + xdc wire.xdc + sources wire.v +) + +add_interchange_test( + name wire_arty + part xc7a35tcsg324-1 + package csg324 + tcl run.tcl + xdc wire.xdc + sources wire.v +) diff --git a/fpga_interchange/examples/tests/wire/run.tcl b/fpga_interchange/examples/tests/wire/run.tcl new file mode 100644 index 00000000..b8d0df72 --- /dev/null +++ b/fpga_interchange/examples/tests/wire/run.tcl @@ -0,0 +1,14 @@ +yosys -import + +read_verilog $::env(SOURCES) + +synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp + +# opt_expr -undriven makes sure all nets are driven, if only by the $undef +# net. +opt_expr -undriven +opt_clean + +setundef -zero -params + +write_json $::env(OUT_JSON) diff --git a/fpga_interchange/examples/tests/wire/wire.v b/fpga_interchange/examples/tests/wire/wire.v new file mode 100644 index 00000000..429d05ff --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire.v @@ -0,0 +1,5 @@ +module top(input i, output o); + +assign o = i; + +endmodule diff --git a/fpga_interchange/examples/tests/wire/wire.xdc b/fpga_interchange/examples/tests/wire/wire.xdc new file mode 100644 index 00000000..c923f0fc --- /dev/null +++ b/fpga_interchange/examples/tests/wire/wire.xdc @@ -0,0 +1,5 @@ +set_property PACKAGE_PIN N16 [get_ports i] +set_property PACKAGE_PIN N15 [get_ports o] + +set_property IOSTANDARD LVCMOS33 [get_ports i] +set_property IOSTANDARD LVCMOS33 [get_ports o] |