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-rw-r--r--fpga_interchange/examples/archcheck/Makefile7
-rw-r--r--fpga_interchange/examples/archcheck/test_data.yaml29
-rw-r--r--fpga_interchange/examples/const_wire/Makefile8
-rw-r--r--fpga_interchange/examples/const_wire/run.tcl14
-rw-r--r--fpga_interchange/examples/const_wire/wire.v8
-rw-r--r--fpga_interchange/examples/const_wire/wire.xdc9
-rw-r--r--fpga_interchange/examples/create_bba/Makefile18
-rw-r--r--fpga_interchange/examples/ff/Makefile8
-rw-r--r--fpga_interchange/examples/ff/ff.v11
-rw-r--r--fpga_interchange/examples/ff/ff.xdc9
-rw-r--r--fpga_interchange/examples/ff/run.tcl14
-rw-r--r--fpga_interchange/examples/template.mk27
-rw-r--r--fpga_interchange/examples/wire/wire.xdc3
13 files changed, 157 insertions, 8 deletions
diff --git a/fpga_interchange/examples/archcheck/Makefile b/fpga_interchange/examples/archcheck/Makefile
index cf82013b..02e1c08e 100644
--- a/fpga_interchange/examples/archcheck/Makefile
+++ b/fpga_interchange/examples/archcheck/Makefile
@@ -13,4 +13,11 @@ check: check_test_data
check_test_data:
$(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
+ --package $(PACKAGE) \
+ --run $(NEXTPNR_PATH)/python/check_arch_api.py
+
+debug_check_test_data:
+ gdb --args $(NEXTPNR_BIN) \
+ --chipdb $(BBA_PATH) \
+ --package $(PACKAGE) \
--run $(NEXTPNR_PATH)/python/check_arch_api.py
diff --git a/fpga_interchange/examples/archcheck/test_data.yaml b/fpga_interchange/examples/archcheck/test_data.yaml
index b41112cf..268d180a 100644
--- a/fpga_interchange/examples/archcheck/test_data.yaml
+++ b/fpga_interchange/examples/archcheck/test_data.yaml
@@ -1,7 +1,36 @@
pip_test:
- src_wire: CLBLM_R_X11Y93/CLBLM_L_D3
dst_wire: SLICE_X15Y93.SLICEL/D3
+pip_chain_test:
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - TIEOFF_X3Y145.TIEOFF/$GND_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD0GND_HARD0
+ - INT_R_X3Y145/GND_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - TIEOFF_X3Y145.TIEOFF/$VCC_SITE_WIRE
+ - TIEOFF_X3Y145.TIEOFF/HARD1VCC_HARD1
+ - INT_R_X3Y145/VCC_WIRE
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - $CONSTANTS_X0Y0/$VCC_NODE
+ - SLICE_X3Y145.SLICEL/$VCC_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/CEUSEDVCC_HARD1
+ - wires:
+ - $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - $CONSTANTS_X0Y0/$GND_NODE
+ - SLICE_X3Y145.SLICEL/$GND_SITE_WIRE
+ - SLICE_X3Y145.SLICEL/SRUSEDGND_HARD0
bel_pin_test:
- bel: SLICE_X15Y93.SLICEL/D6LUT
pin: A3
wire: SLICE_X15Y93.SLICEL/D3
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/GND
+ pin: G
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$GND_SOURCE
+ - bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
+ pin: P
+ wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
diff --git a/fpga_interchange/examples/const_wire/Makefile b/fpga_interchange/examples/const_wire/Makefile
new file mode 100644
index 00000000..49194f53
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/Makefile
@@ -0,0 +1,8 @@
+DESIGN := wire
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/wire.json: wire.v | build
+ yosys -c run.tcl
diff --git a/fpga_interchange/examples/const_wire/run.tcl b/fpga_interchange/examples/const_wire/run.tcl
new file mode 100644
index 00000000..9127be20
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog wire.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/wire.json
diff --git a/fpga_interchange/examples/const_wire/wire.v b/fpga_interchange/examples/const_wire/wire.v
new file mode 100644
index 00000000..5b1ab692
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/wire.v
@@ -0,0 +1,8 @@
+module top(output o, output o2, output o3, output o4);
+
+assign o = 1'b0;
+assign o2 = 1'b1;
+assign o3 = 1'b0;
+assign o4 = 1'b1;
+
+endmodule
diff --git a/fpga_interchange/examples/const_wire/wire.xdc b/fpga_interchange/examples/const_wire/wire.xdc
new file mode 100644
index 00000000..0d96fc45
--- /dev/null
+++ b/fpga_interchange/examples/const_wire/wire.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN N15 [get_ports o]
+set_property PACKAGE_PIN N16 [get_ports o2]
+set_property PACKAGE_PIN P17 [get_ports o3]
+set_property PACKAGE_PIN R17 [get_ports o4]
+
+set_property IOSTANDARD LVCMOS33 [get_ports o]
+set_property IOSTANDARD LVCMOS33 [get_ports o2]
+set_property IOSTANDARD LVCMOS33 [get_ports o3]
+set_property IOSTANDARD LVCMOS33 [get_ports o4]
diff --git a/fpga_interchange/examples/create_bba/Makefile b/fpga_interchange/examples/create_bba/Makefile
index 3033daca..c29bfa82 100644
--- a/fpga_interchange/examples/create_bba/Makefile
+++ b/fpga_interchange/examples/create_bba/Makefile
@@ -30,7 +30,7 @@ include ../common.mk
.DELETE_ON_ERROR:
-.PHONY: all chipdb
+.PHONY: all chipdb test debug_test
all: chipdb
@@ -38,11 +38,7 @@ build:
mkdir build
build/RapidWright: | build
- # FIXME: Update URL / branch as fixes are merged upstream and / or
- # interchange branch on Xilinx/RapidWright is merged to master branch.
- #
- #cd build && git clone -b interchange https://github.com/Xilinx/RapidWright.git
- cd build && git clone -b move_strlist https://github.com/litghost/RapidWright.git
+ cd build && git clone https://github.com/Xilinx/RapidWright.git
build/env: | build
python3 -mvenv build/env
@@ -66,7 +62,7 @@ $(NEXTPNR_PATH)/build/bba/bbasm: | $(NEXTPNR_PATH)/build
cd $(NEXTPNR_PATH)/build && cmake -DARCH=fpga_interchange ..
make -j -C $(NEXTPNR_PATH)/build
-$(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
+build/nextpnr/fpga_interchange/chipdb.bba: build/.setup
mkdir -p build/nextpnr/fpga_interchange
source build/env/bin/activate && \
cd build/python-fpga-interchange/ && \
@@ -76,7 +72,7 @@ $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba: build/.setup
RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
INTERCHANGE_PATH=$(INTERCHANGE_PATH)
-$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm $(NEXTPNR_PATH)/fpga_interchange/chipdb.bba
+$(BBA_PATH): $(NEXTPNR_PATH)/build/bba/bbasm build/nextpnr/fpga_interchange/chipdb.bba
$(NEXTPNR_PATH)/build/bba/bbasm -l build/nextpnr/fpga_interchange/chipdb.bba $(BBA_PATH)
chipdb: $(BBA_PATH)
@@ -87,5 +83,11 @@ test: chipdb
--package csg324 \
--test
+debug_test: chipdb
+ gdb --args $(NEXTPNR_PATH)/build/nextpnr-fpga_interchange \
+ --chipdb $(BBA_PATH) \
+ --package csg324 \
+ --test
+
clean:
rm -rf build
diff --git a/fpga_interchange/examples/ff/Makefile b/fpga_interchange/examples/ff/Makefile
new file mode 100644
index 00000000..c6118ff7
--- /dev/null
+++ b/fpga_interchange/examples/ff/Makefile
@@ -0,0 +1,8 @@
+DESIGN := ff
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/ff.json: ff.v | build
+ yosys -c run.tcl
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+ if(r)
+ q <= 1'b0;
+ else
+ q <= d;
+end
+
+endmodule
diff --git a/fpga_interchange/examples/ff/ff.xdc b/fpga_interchange/examples/ff/ff.xdc
new file mode 100644
index 00000000..3c132f1d
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property PACKAGE_PIN N15 [get_ports d]
+set_property PACKAGE_PIN N16 [get_ports r]
+set_property PACKAGE_PIN M17 [get_ports q]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports d]
+set_property IOSTANDARD LVCMOS33 [get_ports r]
+set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/ff/run.tcl b/fpga_interchange/examples/ff/run.tcl
new file mode 100644
index 00000000..726d86eb
--- /dev/null
+++ b/fpga_interchange/examples/ff/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog ff.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/ff.json
diff --git a/fpga_interchange/examples/template.mk b/fpga_interchange/examples/template.mk
index 819cdb1f..c795544e 100644
--- a/fpga_interchange/examples/template.mk
+++ b/fpga_interchange/examples/template.mk
@@ -46,6 +46,24 @@ build/$(DESIGN)_phys.yaml: build/$(DESIGN).phys
phys_yaml: build/$(DESIGN)_phys.yaml
+verbose: build/$(DESIGN).netlist
+ $(NEXTPNR_BIN) \
+ --chipdb $(BBA_PATH) \
+ --xdc $(DESIGN).xdc \
+ --netlist build/$(DESIGN).netlist \
+ --phys build/$(DESIGN).phys \
+ --package $(PACKAGE) \
+ --verbose
+
+verbose2: build/$(DESIGN).netlist
+ $(NEXTPNR_BIN) \
+ --chipdb $(BBA_PATH) \
+ --xdc $(DESIGN).xdc \
+ --netlist build/$(DESIGN).netlist \
+ --phys build/$(DESIGN).phys \
+ --package $(PACKAGE) \
+ --debug
+
debug: build/$(DESIGN).netlist
gdb --args $(NEXTPNR_BIN) \
--chipdb $(BBA_PATH) \
@@ -54,6 +72,15 @@ debug: build/$(DESIGN).netlist
--phys build/$(DESIGN).phys \
--package $(PACKAGE)
+debug_verbose: build/$(DESIGN).netlist
+ gdb --args $(NEXTPNR_BIN) \
+ --chipdb $(BBA_PATH) \
+ --xdc $(DESIGN).xdc \
+ --netlist build/$(DESIGN).netlist \
+ --phys build/$(DESIGN).phys \
+ --package $(PACKAGE) \
+ --verbose
+
build/$(DESIGN).dcp: build/$(DESIGN).netlist build/$(DESIGN).phys $(DESIGN).xdc
RAPIDWRIGHT_PATH=$(RAPIDWRIGHT_PATH) \
$(RAPIDWRIGHT_PATH)/scripts/invoke_rapidwright.sh \
diff --git a/fpga_interchange/examples/wire/wire.xdc b/fpga_interchange/examples/wire/wire.xdc
index e1fce5f0..c923f0fc 100644
--- a/fpga_interchange/examples/wire/wire.xdc
+++ b/fpga_interchange/examples/wire/wire.xdc
@@ -1,2 +1,5 @@
set_property PACKAGE_PIN N16 [get_ports i]
set_property PACKAGE_PIN N15 [get_ports o]
+
+set_property IOSTANDARD LVCMOS33 [get_ports i]
+set_property IOSTANDARD LVCMOS33 [get_ports o]
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 19:18:20 +0000