1 files changed, 20 insertions, 34 deletions

diff --git a/fpga_interchange/fpga_interchange.cpp b/fpga_interchange/fpga_interchange.cpp
index cf89ef1c..1d08b128 100644
--- a/fpga_interchange/fpga_interchange.cpp
+++ b/fpga_interchange/fpga_interchange.cpp
@@ -43,7 +43,7 @@ static void write_message(::capnp::MallocMessageBuilder & message, const std::st
 
 struct StringEnumerator {
     std::vector<std::string> strings;
-    std::unordered_map<std::string, size_t> string_to_index;
+    dict<std::string, size_t> string_to_index;
 
     size_t get_index(const std::string &s) {
         auto result = string_to_index.emplace(s, strings.size());
@@ -59,7 +59,7 @@ struct StringEnumerator {
 static PhysicalNetlist::PhysNetlist::RouteBranch::Builder emit_branch(
         const Context * ctx,
         StringEnumerator * strings,
-        const std::unordered_map<PipId, PlaceStrength> &pip_place_strength,
+        const dict<PipId, PlaceStrength> &pip_place_strength,
         PipId pip,
         PhysicalNetlist::PhysNetlist::RouteBranch::Builder branch) {
     if(ctx->is_pip_synthetic(pip)) {
@@ -264,10 +264,10 @@ static void init_bel_pin(
 static void emit_net(
         const Context * ctx,
         StringEnumerator * strings,
-        const std::unordered_map<WireId, std::vector<PipId>> &pip_downhill,
-        const std::unordered_map<WireId, std::vector<BelPin>> &sinks,
-        std::unordered_set<PipId> *pips,
-        const std::unordered_map<PipId, PlaceStrength> &pip_place_strength,
+        const dict<WireId, std::vector<PipId>> &pip_downhill,
+        const dict<WireId, std::vector<BelPin>> &sinks,
+        pool<PipId> *pips,
+        const dict<PipId, PlaceStrength> &pip_place_strength,
         WireId wire, PhysicalNetlist::PhysNetlist::RouteBranch::Builder branch) {
     size_t number_branches = 0;
 
@@ -349,7 +349,7 @@ static PhysicalNetlist::PhysNetlist::RouteBranch::Builder init_local_source(
         StringEnumerator * strings,
         PhysicalNetlist::PhysNetlist::RouteBranch::Builder source_branch,
         PipId root,
-        const std::unordered_map<PipId, PlaceStrength> &pip_place_strength,
+        const dict<PipId, PlaceStrength> &pip_place_strength,
         WireId *root_wire) {
     WireId source_wire = ctx->getPipSrcWire(root);
     BelPin source_bel_pin = find_source(ctx, source_wire);
@@ -365,7 +365,7 @@ static PhysicalNetlist::PhysNetlist::RouteBranch::Builder init_local_source(
 }
 
 static void find_non_synthetic_edges(const Context * ctx, WireId root_wire,
-        const std::unordered_map<WireId, std::vector<PipId>> &pip_downhill,
+        const dict<WireId, std::vector<PipId>> &pip_downhill,
         std::vector<PipId> *root_pips) {
     std::vector<WireId> wires_to_expand;
 
@@ -403,7 +403,7 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str
 
     phys_netlist.setPart(ctx->get_part());
 
-    std::unordered_set<IdString> placed_cells;
+    pool<IdString> placed_cells;
     for(const auto & cell_pair : ctx->cells) {
         const CellInfo & cell = *cell_pair.second;
         if(cell.bel == BelId()) {
@@ -444,7 +444,7 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str
 
     std::vector<IdString> ports;
 
-    std::unordered_map<std::string, std::string> sites;
+    dict<std::string, std::string> sites;
     auto placements = phys_netlist.initPlacements(number_placements);
     auto placement_iter = placements.begin();
 
@@ -556,9 +556,9 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str
             net_out.setName(strings.get_index(net.name.str(ctx)));
         }
 
-        std::unordered_map<WireId, BelPin> root_wires;
-        std::unordered_map<WireId, std::vector<PipId>> pip_downhill;
-        std::unordered_set<PipId> pips;
+        dict<WireId, BelPin> root_wires;
+        dict<WireId, std::vector<PipId>> pip_downhill;
+        pool<PipId> pips;
 
         if (driver_cell != nullptr && driver_cell->bel != BelId() && ctx->isBelLocationValid(driver_cell->bel)) {
             for(IdString bel_pin_name : driver_cell->cell_bel_pins.at(net.driver.port)) {
@@ -573,7 +573,7 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str
             }
         }
 
-        std::unordered_map<WireId, std::vector<BelPin>> sinks;
+        dict<WireId, std::vector<BelPin>> sinks;
         for(const auto &port_ref : net.users) {
             if(port_ref.cell != nullptr && port_ref.cell->bel != BelId() && ctx->isBelLocationValid(port_ref.cell->bel)) {
                 auto pin_iter = port_ref.cell->cell_bel_pins.find(port_ref.port);
@@ -598,7 +598,7 @@ void FpgaInterchange::write_physical_netlist(const Context * ctx, const std::str
             }
         }
 
-        std::unordered_map<PipId, PlaceStrength> pip_place_strength;
+        dict<PipId, PlaceStrength> pip_place_strength;
 
         for(auto &wire_pair : net.wires) {
             WireId downhill_wire = wire_pair.first;
@@ -723,23 +723,11 @@ struct PortKey {
     bool operator == (const PortKey &other) const {
         return inst_idx == other.inst_idx && port_idx == other.port_idx;
     }
-};
-
-NEXTPNR_NAMESPACE_END
-
-template <> struct std::hash<NEXTPNR_NAMESPACE_PREFIX PortKey>
-{
-    std::size_t operator()(const NEXTPNR_NAMESPACE_PREFIX PortKey &key) const noexcept
-    {
-        std::size_t seed = 0;
-        boost::hash_combine(seed, std::hash<int32_t>()(key.inst_idx));
-        boost::hash_combine(seed, std::hash<uint32_t>()(key.port_idx));
-        return seed;
+    unsigned int hash() const {
+        return mkhash(inst_idx, port_idx);
     }
 };
 
-NEXTPNR_NAMESPACE_BEGIN
-
 struct ModuleReader {
     const LogicalNetlistImpl *root;
 
@@ -748,9 +736,9 @@ struct ModuleReader {
     LogicalNetlist::Netlist::Cell::Reader cell;
     LogicalNetlist::Netlist::CellDeclaration::Reader cell_decl;
 
-    std::unordered_map<int32_t, LogicalNetlist::Netlist::Net::Reader> net_indicies;
-    std::unordered_map<int32_t, std::string> disconnected_nets;
-    std::unordered_map<PortKey, std::vector<int32_t>> connections;
+    dict<int32_t, LogicalNetlist::Netlist::Net::Reader> net_indicies;
+    dict<int32_t, std::string> disconnected_nets;
+    dict<PortKey, std::vector<int32_t>> connections;
 
     ModuleReader(const LogicalNetlistImpl *root,
             LogicalNetlist::Netlist::CellInstance::Reader cell_inst, bool is_top);
@@ -834,7 +822,6 @@ struct LogicalNetlistImpl
 
     template <typename TFunc> void foreach_netname(const ModuleReader &mod, TFunc Func) const
     {
-        // std::unordered_map<int32_t, LogicalNetlist::Netlist::Net::Reader> net_indicies;
         for(auto net_pair : mod.net_indicies) {
             NetReader net_reader(&mod, net_pair.first);
             auto net = net_pair.second;
@@ -842,7 +829,6 @@ struct LogicalNetlistImpl
             Func(strings.at(net.getName()), net_reader);
         }
 
-        // std::unordered_map<int32_t, IdString> disconnected_nets;
         for(auto net_pair : mod.disconnected_nets) {
             NetReader net_reader(&mod, net_pair.first);
             Func(net_pair.second, net_reader);