1 files changed, 0 insertions, 80 deletions
diff --git a/fpga_interchange/luts.cc b/fpga_interchange/luts.cc
index 2ac3b6da..9c68739e 100644
--- a/fpga_interchange/luts.cc
+++ b/fpga_interchange/luts.cc
@@ -446,86 +446,6 @@ bool LutMapper::remap_luts(const Context *ctx, SiteLutMappingResult* lut_mapping
         lut_mapping->cells.push_back(cell);
     }
 
-/*
-#ifdef DEBUG_LUT_ROTATION
-    log_info("Final mapping:\n");
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        CellInfo *cell = cells[cell_idx];
-        for (auto &cell_pin_pair : cell->cell_bel_pins) {
-            log_info("%s %s %s =>", cell->type.c_str(ctx), cell->name.c_str(ctx), cell_pin_pair.first.c_str(ctx));
-            for (auto bel_pin : cell_pin_pair.second) {
-                log(" %s", bel_pin.c_str(ctx));
-            }
-            log("\n");
-        }
-    }
-#endif
-*/
-
-
-
-
-/*
-
-    // Push new cell -> BEL pin maps out to cells now that equations have been
-    // verified!
-    for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-        CellInfo *cell = cells[cell_idx];
-        auto &lut_bel = *lut_bels[cell_idx];
-
-        for (size_t pin_idx = 0; pin_idx < cell->lut_cell.pins.size(); ++pin_idx) {
-            auto &bel_pins = cell->cell_bel_pins[cell->lut_cell.pins[pin_idx]];
-            bel_pins.clear();
-            bel_pins.push_back(lut_bel.pins[cell_to_bel_pin_remaps[cell_idx][pin_idx]]);
-        }
-    }
-
-    if (cells.size() == element.lut_bels.size()) {
-        for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-            CellInfo *cell = cells[cell_idx];
-            auto &lut_bel = *lut_bels[cell_idx];
-            cell->lut_cell.vcc_pins.clear();
-            for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) {
-                if ((used_pins & (1 << bel_pin_idx)) == 0) {
-                    NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    cell->lut_cell.vcc_pins.emplace(lut_bel.pins.at(bel_pin_idx));
-                }
-            }
-        }
-    } else {
-        // Look to see if wires can be run from element inputs to unused
-        // outputs. If not, block the BEL pin by tying to VCC.
-        //
-        // FIXME: The assumption is that unused pins are tied VCC.
-        // This is not generally true.
-        //
-        // Use Arch::prefered_constant_net_type to determine what
-        // constant net should be used for unused pins.
-        uint32_t vcc_pins = check_wires(bel_to_cell_pin_remaps, lut_bels, used_pins, blocked_luts);
-#if defined(DEBUG_LUT_ROTATION)
-        log_info("vcc_pins = 0x%x", vcc_pins);
-        for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-            CellInfo *cell = cells[cell_idx];
-            log(", %s => %s", ctx->nameOfBel(cell->bel), cell->name.c_str(ctx));
-        }
-        log("\n");
-#endif
-
-        for (size_t cell_idx = 0; cell_idx < cells.size(); ++cell_idx) {
-            CellInfo *cell = cells[cell_idx];
-            auto &lut_bel = *lut_bels[cell_idx];
-            cell->lut_cell.vcc_pins.clear();
-            for (size_t bel_pin_idx = 0; bel_pin_idx < lut_bel.pins.size(); ++bel_pin_idx) {
-                if ((vcc_pins & (1 << bel_pin_idx)) != 0) {
-                    NPNR_ASSERT(bel_to_cell_pin_remaps[cell_idx][bel_pin_idx] == -1);
-                    auto pin = lut_bel.pins.at(bel_pin_idx);
-                    cell->lut_cell.vcc_pins.emplace(pin);
-                }
-            }
-        }
-    }
-*/
-
     return true;
 }