5 files changed, 14 insertions, 12 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 71c68e66..663587fd 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -2047,8 +2047,8 @@ void Arch::pack_default_conns()
 
     std::vector<IdString> dead_nets;
 
-    for (auto cell : sorted(ctx->cells)) {
-        CellInfo *ci = cell.second;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
         const DefaultCellConnsPOD *conns = get_default_conns(ci->type);
         if (conns == nullptr)
             continue;
diff --git a/fpga_interchange/arch_pybindings.cc b/fpga_interchange/arch_pybindings.cc
index 68619866..03b20841 100644
--- a/fpga_interchange/arch_pybindings.cc
+++ b/fpga_interchange/arch_pybindings.cc
@@ -49,10 +49,10 @@ void arch_wrap_python(py::module &m)
     fn_wrapper_1a_v<Context, decltype(&Context::explain_bel_status), &Context::explain_bel_status,
                     conv_from_str<BelId>>::def_wrap(ctx_cls, "explain_bel_status");
 
-    typedef std::unordered_map<IdString, std::unique_ptr<CellInfo>> CellMap;
-    typedef std::unordered_map<IdString, std::unique_ptr<NetInfo>> NetMap;
-    typedef std::unordered_map<IdString, IdString> AliasMap;
-    typedef std::unordered_map<IdString, HierarchicalCell> HierarchyMap;
+    typedef dict<IdString, std::unique_ptr<CellInfo>> CellMap;
+    typedef dict<IdString, std::unique_ptr<NetInfo>> NetMap;
+    typedef dict<IdString, IdString> AliasMap;
+    typedef dict<IdString, HierarchicalCell> HierarchyMap;
 
     auto belpin_cls = py::class_<ContextualWrapper<BelPin>>(m, "BelPin");
     readonly_wrapper<BelPin, decltype(&BelPin::bel), &BelPin::bel, conv_to_str<BelId>>::def_wrap(belpin_cls, "bel");
diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h
index aa3f1e6e..ba4fe054 100644
--- a/fpga_interchange/archdefs.h
+++ b/fpga_interchange/archdefs.h
@@ -85,12 +85,14 @@ struct GroupId
 {
     bool operator==(const GroupId &other) const { return true; }
     bool operator!=(const GroupId &other) const { return false; }
+    unsigned int hash() const { return 0; }
 };
 
 struct DecalId
 {
     bool operator==(const DecalId &other) const { return true; }
     bool operator!=(const DecalId &other) const { return false; }
+    unsigned int hash() const { return 0; }
 };
 
 struct BelBucketId
diff --git a/fpga_interchange/globals.cc b/fpga_interchange/globals.cc
index 66d04f75..918b916e 100644
--- a/fpga_interchange/globals.cc
+++ b/fpga_interchange/globals.cc
@@ -160,8 +160,8 @@ void Arch::place_globals()
 
     // TODO: for more complex PLL type setups, we might want a toposort or iterative loop as the PLL must be placed
     // before the GBs it drives
-    for (auto cell : sorted(ctx->cells)) {
-        CellInfo *ci = cell.second;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
         const GlobalCellPOD *glb_cell = global_cell_info(ci->type);
         if (glb_cell == nullptr)
             continue;
@@ -239,8 +239,8 @@ void Arch::route_globals()
     IdString gnd_net_name(chip_info->constants->gnd_net_name);
     IdString vcc_net_name(chip_info->constants->vcc_net_name);
 
-    for (auto cell : sorted(ctx->cells)) {
-        CellInfo *ci = cell.second;
+    for (auto &cell : ctx->cells) {
+        CellInfo *ci = cell.second.get();
         const GlobalCellPOD *glb_cell = global_cell_info(ci->type);
         if (glb_cell == nullptr)
             continue;
diff --git a/fpga_interchange/macros.cc b/fpga_interchange/macros.cc
index eee35d9f..8339829f 100644
--- a/fpga_interchange/macros.cc
+++ b/fpga_interchange/macros.cc
@@ -53,8 +53,8 @@ void Arch::expand_macros()
     // Make up a list of cells, so we don't have modify-while-iterating issues
     Context *ctx = getCtx();
     std::vector<CellInfo *> cells;
-    for (auto cell : sorted(ctx->cells))
-        cells.push_back(cell.second);
+    for (auto &cell : ctx->cells)
+        cells.push_back(cell.second.get());
 
     std::vector<CellInfo *> next_cells;