diff options
Diffstat (limited to 'generic/examples')
| -rw-r--r-- | generic/examples/README.md | 2 | ||||
| -rwxr-xr-x | generic/examples/simple.sh | 2 | ||||
| -rw-r--r-- | generic/examples/simple_timing.py | 15 |
3 files changed, 18 insertions, 1 deletions
diff --git a/generic/examples/README.md b/generic/examples/README.md index 4641f542..dd154a51 100644 --- a/generic/examples/README.md +++ b/generic/examples/README.md @@ -4,6 +4,8 @@ This contains a simple, artificial, example of the nextpnr generic API. - simple.py procedurally generates a simple FPGA architecture with IO at the edges, logic slices in all other tiles, and interconnect only between adjacent tiles + + - simple_timing.py annotates cells with timing data (this is a separate script that must be run after packing) - report.py stores design information after place-and-route to blinky.txt in place of real bitstream generation diff --git a/generic/examples/simple.sh b/generic/examples/simple.sh index ed800639..2e8d6180 100755 --- a/generic/examples/simple.sh +++ b/generic/examples/simple.sh @@ -1,4 +1,4 @@ #!/usr/bin/bash set -ex yosys -p "tcl ../synth/synth_generic.tcl 4 blinky.json" blinky.v -../../nextpnr-generic --pre-pack simple.py --json blinky.json --post-route report.py
\ No newline at end of file +../../nextpnr-generic --pre-pack simple.py --pre-place simple_timing.py --json blinky.json --post-route report.py
\ No newline at end of file diff --git a/generic/examples/simple_timing.py b/generic/examples/simple_timing.py new file mode 100644 index 00000000..a955c8d7 --- /dev/null +++ b/generic/examples/simple_timing.py @@ -0,0 +1,15 @@ +for cname, cell in ctx.cells: + if cell.type != "GENERIC_SLICE": + continue + if cname in ("$PACKER_GND", "$PACKER_VCC"): + continue + K = int(cell.params["K"]) + if cell.params["FF_USED"] == "1": + ctx.addCellTimingClock(cell=cname, port="CLK") + for i in range(K): + ctx.addCellTimingSetupHold(cell=cname, port="I[%d]" % i, clock="CLK", + setup=ctx.getDelayFromNS(0.2), hold=ctx.getDelayFromNS(0)) + ctx.addCellTimingClockToOut(cell=cname, port="Q", clock="CLK", clktoq=ctx.getDelayFromNS(0.2)) + else: + for i in range(K): + ctx.addCellTimingDelay(cell=cname, fromPort="I[%d]" % i, toPort="Q", delay=ctx.getDelayFromNS(0.2))
\ No newline at end of file |