1 files changed, 36 insertions, 13 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index e9a7d2b6..65b21afd 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -19,13 +19,13 @@
 
 #include <algorithm>
 #include <cmath>
+#include "cells.h"
 #include "gfx.h"
 #include "log.h"
 #include "nextpnr.h"
 #include "placer1.h"
 #include "router1.h"
 #include "util.h"
-#include "cells.h"
 NEXTPNR_NAMESPACE_BEGIN
 
 // -----------------------------------------------------------------------
@@ -279,17 +279,11 @@ BelRange Arch::getBelsByTile(int x, int y) const
     // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used
     BelRange br;
 
-    Loc loc;
-    loc.x = x;
-    loc.y = y;
-    loc.z = 0;
-
-    br.b.cursor = Arch::getBelByLocation(loc).index;
+    br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index;
     br.e.cursor = br.b.cursor;
 
     if (br.e.cursor != -1) {
-        while (br.e.cursor < chip_info->num_bels &&
-               chip_info->bel_data[br.e.cursor].x == x &&
+        while (br.e.cursor < chip_info->num_bels && chip_info->bel_data[br.e.cursor].x == x &&
                chip_info->bel_data[br.e.cursor].y == y)
             br.e.cursor++;
     }
@@ -314,7 +308,21 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
     return br;
 }
 
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
+PortType Arch::getBelPinType(BelId bel, PortPin pin) const
+{
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        if (bel_wires[i].port == pin)
+            return PortType(bel_wires[i].type);
+
+    return PORT_INOUT;
+}
+
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
 {
     WireId ret;
 
@@ -332,6 +340,21 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
     return ret;
 }
 
+std::vector<PortPin> Arch::getBelPins(BelId bel) const
+{
+    std::vector<PortPin> ret;
+
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        ret.push_back(bel_wires[i].port);
+
+    return ret;
+}
+
 // -----------------------------------------------------------------------
 
 WireId Arch::getWireByName(IdString name) const
@@ -525,9 +548,9 @@ DecalXY Arch::getWireDecal(WireId wire) const
 DecalXY Arch::getPipDecal(PipId pip) const
 {
     DecalXY decalxy;
-    // decalxy.decal.type = DecalId::TYPE_PIP;
-    // decalxy.decal.index = pip.index;
-    // decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
+    decalxy.decal.type = DecalId::TYPE_PIP;
+    decalxy.decal.index = pip.index;
+    decalxy.decal.active = pip_to_net.at(pip.index) != IdString();
     return decalxy;
 };