diff options
Diffstat (limited to 'ice40/arch.h')
| -rw-r--r-- | ice40/arch.h | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index 356f88da..85fb9fc0 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -63,6 +63,17 @@ enum PortPin : int32_t PIN_MAXIDX }; +enum WireType : int8_t +{ + WIRE_TYPE_NONE = 0, + WIRE_TYPE_LOCAL = 1, + WIRE_TYPE_GLOBAL = 2, + WIRE_TYPE_SP4_VERT = 3, + WIRE_TYPE_SP4_HORZ = 4, + WIRE_TYPE_SP12_HORZ = 5, + WIRE_TYPE_SP12_VERT = 6 +}; + // ----------------------------------------------------------------------- /**** Everything in this section must be kept in sync with chipdb.py ****/ @@ -130,7 +141,9 @@ struct WireInfoPOD BelPortPOD bel_uphill; RelPtr<BelPortPOD> bels_downhill; - int16_t x, y; + int8_t x, y; + WireType type; + int8_t padding_0; } __attribute__((packed)); struct PackagePinPOD @@ -740,8 +753,10 @@ struct Arch : BaseCtx // ------------------------------------------------- - bool estimatePosition(BelId bel, int &x, int &y) const; + void estimatePosition(BelId bel, int &x, int &y, bool &gb) const; delay_t estimateDelay(WireId src, WireId dst) const; + delay_t getDelayEpsilon() const { return 10; } + float getDelayNS(delay_t v) const { return v * 0.001; } // ------------------------------------------------- |