diff options
Diffstat (limited to 'ice40/pack.cc')
| -rw-r--r-- | ice40/pack.cc | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/ice40/pack.cc b/ice40/pack.cc index fc182e98..e7fdc627 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -23,6 +23,7 @@ #include <iterator> #include <unordered_set> #include "cells.h" +#include "chains.h" #include "design_utils.h" #include "log.h" #include "util.h" @@ -444,7 +445,8 @@ static bool is_logic_port(BaseCtx *ctx, const PortRef &port) { if (is_clock_port(ctx, port) || is_reset_port(ctx, port) || is_enable_port(ctx, port)) return false; - return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && port.cell->type != ctx->id("SB_GB"); + return !is_sb_io(ctx, port.cell) && !is_sb_pll40(ctx, port.cell) && !is_sb_pll40_pad(ctx, port.cell) && + port.cell->type != ctx->id("SB_GB"); } static void insert_global(Context *ctx, NetInfo *net, bool is_reset, bool is_cen, bool is_logic) @@ -893,6 +895,8 @@ bool Arch::pack() pack_ram(ctx); pack_special(ctx); ctx->assignArchInfo(); + constrain_chains(ctx); + ctx->assignArchInfo(); log_info("Checksum: 0x%08x\n", ctx->checksum()); return true; } catch (log_execution_error_exception) { |