diff options
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.cc | 22 | ||||
| -rw-r--r-- | ice40/arch.h | 14 |
2 files changed, 20 insertions, 16 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index 324934d0..16104033 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -291,7 +291,8 @@ BelId Arch::getBelByLocation(Loc loc) const BelRange Arch::getBelsByTile(int x, int y) const { - // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates are used + // In iCE40 chipdb bels at the same tile are consecutive and dense z ordinates + // are used BelRange br; br.b.cursor = Arch::getBelByLocation(Loc(x, y, 0)).index; @@ -645,23 +646,27 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay auto sink_loc = getBelLocation(sink.cell->bel); if (driver_loc.y == sink_loc.y) budget = 0; - else switch (args.type) { + else + switch (args.type) { #ifndef ICE40_HX1K_ONLY case ArchArgs::HX8K: #endif case ArchArgs::HX1K: - budget = 190; break; + budget = 190; + break; #ifndef ICE40_HX1K_ONLY case ArchArgs::LP384: case ArchArgs::LP1K: case ArchArgs::LP8K: - budget = 290; break; + budget = 290; + break; case ArchArgs::UP5K: - budget = 560; break; + budget = 560; + break; #endif default: log_error("Unsupported iCE40 chip type.\n"); - } + } return true; } return false; @@ -913,10 +918,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out; } -bool Arch::isIOCell(const CellInfo *cell) const -{ - return cell->type == id_sb_io; -} +bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id_sb_io; } // Assign arch arg info void Arch::assignArchInfo() diff --git a/ice40/arch.h b/ice40/arch.h index 2b785079..a5be7e33 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -400,10 +400,10 @@ struct Arch : BaseCtx mutable std::unordered_map<Loc, int> bel_by_loc; std::vector<bool> bel_carry; - std::vector<CellInfo*> bel_to_cell; - std::vector<NetInfo*> wire_to_net; - std::vector<NetInfo*> pip_to_net; - std::vector<NetInfo*> switches_locked; + std::vector<CellInfo *> bel_to_cell; + std::vector<NetInfo *> wire_to_net; + std::vector<NetInfo *> pip_to_net; + std::vector<NetInfo *> switches_locked; ArchArgs args; Arch(ArchArgs args); @@ -799,7 +799,8 @@ struct Arch : BaseCtx // ------------------------------------------------- - // Perform placement validity checks, returning false on failure (all implemented in arch_place.cc) + // Perform placement validity checks, returning false on failure (all + // implemented in arch_place.cc) // Whether or not a given cell can be placed at a given Bel // This is not intended for Bel type checks, but finer-grained constraints @@ -813,7 +814,8 @@ struct Arch : BaseCtx bool logicCellsCompatible(const std::vector<const CellInfo *> &cells) const; // ------------------------------------------------- - // Assign architecure-specific arguments to nets and cells, which must be called between packing or further + // Assign architecure-specific arguments to nets and cells, which must be + // called between packing or further // netlist modifications, and validity checks void assignArchInfo(); void assignCellInfo(CellInfo *cell); |