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-rw-r--r--machxo2/synth/synth_machxo2.tcl24
1 files changed, 0 insertions, 24 deletions
diff --git a/machxo2/synth/synth_machxo2.tcl b/machxo2/synth/synth_machxo2.tcl
deleted file mode 100644
index e5d88e0d..00000000
--- a/machxo2/synth/synth_machxo2.tcl
+++ /dev/null
@@ -1,24 +0,0 @@
-# Usage
-# tcl synth_generic.tcl {K} {out.json}
-
-set LUT_K 4
-if {$argc > 0} { set LUT_K [lindex $argv 0] }
-yosys read_verilog -lib [file dirname [file normalize $argv0]]/prims.v
-yosys hierarchy -check
-yosys proc
-yosys flatten
-yosys tribuf -logic
-yosys deminout
-yosys synth -run coarse
-yosys memory_map
-yosys opt -full
-yosys techmap -map +/techmap.v
-yosys opt -fast
-yosys abc -lut $LUT_K -dress
-yosys clean
-yosys techmap -D LUT_K=$LUT_K -map [file dirname [file normalize $argv0]]/cells_map.v
-yosys clean
-yosys hierarchy -check
-yosys stat
-
-if {$argc > 1} { yosys write_json [lindex $argv 1] }