aboutsummaryrefslogtreecommitdiffstats
path: root/mistral/bitstream.cc
diff options
context:
space:
mode:
Diffstat (limited to 'mistral/bitstream.cc')
-rw-r--r--mistral/bitstream.cc156
1 files changed, 37 insertions, 119 deletions
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index eed508b3..340f4b96 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -29,129 +29,41 @@ struct MistralBitgen
Context *ctx;
CycloneV *cv;
- void init()
- {
- ctx->init_base_bitstream();
- // Default options
- cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
- if (!ctx->setting<bool>("compress_rbf", false))
- cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
- cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
- cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
- cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
- cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
- cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
- cv->opt_b_set(CycloneV::NCEO_DIS, true);
- cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
- cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
- if (!ctx->setting<bool>("compress_rbf", false))
- cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
- else
- cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
- cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
- cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
- cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
- // Default inversion
- write_default_inv();
- }
+ using rnode_t = CycloneV::rnode_t;
+ using pnode_t = CycloneV::pnode_t;
+ using pos_t = CycloneV::pos_t;
+ using block_type_t = CycloneV::block_type_t;
+ using port_type_t = CycloneV::port_type_t;
- void write_default_inv()
+ rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
{
- // Some PNODEs are inverted by default. Set them up here.
- for (const auto &pn2r : cv->get_all_p2r()) {
- const auto &pn = pn2r.first;
- auto pt = CycloneV::pn2pt(pn);
- auto pi = CycloneV::pn2pi(pn);
+ auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
+ auto rn1 = cv->pnode_to_rnode(pn1);
+ if(rn1)
+ return rn1;
- switch (CycloneV::pn2bt(pn)) {
- case CycloneV::HMC: {
- // HMC OE are inverted to set OE=0, i.e. unused pins floating
- // TODO: handle the case when we are using the HMC or HMC bypass
- std::string name(CycloneV::port_type_names[pt]);
- if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
- continue;
- cv->inv_set(pn2r.second, true);
- break;
- };
- // HPS IO - TODO: what about when we actually support the HPS primitives?
- case CycloneV::HPS_BOOT: {
- switch (pt) {
- case CycloneV::CSEL_EN:
- case CycloneV::BSEL_EN:
- case CycloneV::BOOT_FROM_FPGA_READY:
- case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
- cv->inv_set(pn2r.second, true);
- break;
- case CycloneV::CSEL:
- if (pi < 2)
- cv->inv_set(pn2r.second, true);
- break;
- case CycloneV::BSEL:
- if (pi < 3)
- cv->inv_set(pn2r.second, true);
- break;
- default:
- break;
- };
- break;
- };
- case CycloneV::HPS_CROSS_TRIGGER: {
- if (pt == CycloneV::CLK_EN)
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::HPS_TEST: {
- if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::GPIO: {
- // Ignore GPIO used by the design
- BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
- CycloneV::pn2bi(pn));
- if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
- continue;
- // Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
- // Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
- // GND, presumably for power/EMI reasons
- bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
- if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
- continue;
- if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
- continue;
- cv->inv_set(pn2r.second, true);
- break;
- };
- case CycloneV::FPLL: {
- if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
- cv->inv_set(pn2r.second, true);
- break;
- };
- default:
- break;
+ if(bt == CycloneV::GPIO) {
+ auto pn2 = cv->p2p_to(pn1);
+ if(!pn2) {
+ auto pnv = cv->p2p_from(pn1);
+ if(!pnv.empty())
+ pn2 = pnv[0];
}
+ auto pn3 = cv->hmc_get_bypass(pn2);
+ auto rn2 = cv->pnode_to_rnode(pn3);
+ return rn2;
}
+
+ return 0;
}
- void write_dqs()
+ void options()
{
- for (auto pos : cv->dqs16_get_pos()) {
- int x = CycloneV::pos2x(pos), y = CycloneV::pos2y(pos);
- // DQS bypass for used output pins
- for (int z = 0; z < 16; z++) {
- int ioy = y + (z / 4) - 2;
- if (ioy < 0 || ioy >= int(cv->get_tile_sy()))
- continue;
- BelId bel = ctx->bel_by_block_idx(x, ioy, id_MISTRAL_IO, z % 4);
- if (bel == BelId())
- continue;
- CellInfo *ci = ctx->getBoundBelCell(bel);
- if (ci == nullptr || (ci->type != id_MISTRAL_IO && ci->type != id_MISTRAL_OB))
- continue; // not an output
- cv->bmux_m_set(CycloneV::DQS16, pos, CycloneV::INPUT_REG4_SEL, z, CycloneV::SEL_LOCKED_DPA);
- cv->bmux_r_set(CycloneV::DQS16, pos, CycloneV::RB_T9_SEL_EREG_CFF_DELAY, z, 0x1f);
- }
- }
+ if (!ctx->setting<bool>("compress_rbf", false)) {
+ cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
+ cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
+ } else
+ cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
}
void write_routing()
@@ -182,12 +94,19 @@ struct MistralBitgen
if (is_output) {
cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::DRIVE_STRENGTH, bi, CycloneV::V3P3_LVTTL_16MA_LVCMOS_2MA);
cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::IOCSR_STD, bi, CycloneV::DIS);
+
+ // Output gpios must also bypass things in the associated dqs
+ auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
+ if(dqs) {
+ cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
+ cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);
+ }
}
// There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
// prevent a single bitflip from turning inputs to outputs and messing up other devices on the boards, notably
// ECP5 does similar. OEIN.0 inverted for outputs; OEIN.1 for inputs
- cv->inv_set(cv->pnode_to_rnode(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, is_output ? 0 : 1)),
- true);
+ cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 0), is_output);
+ cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 1), !is_output);
}
void write_clkbuf_cell(CellInfo *ci, int x, int y, int bi)
@@ -392,9 +311,8 @@ struct MistralBitgen
void run()
{
cv->clear();
- init();
+ options();
write_routing();
- write_dqs();
write_cells();
write_labs();
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 18:50:08 +0000