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* Unbreak CIgatecat2022-12-021-5/+5
* gowin: update the apicula versionYRabbit2022-12-021-1/+1
* Fix python version in CIMiodrag Milanovic2022-10-241-1/+2
* Update CI scriptMiodrag Milanovic2022-10-241-6/+6
* Disable broken and failing interchange CIgatecat2022-06-211-0/+0
* ci: Restructure and move entirely to GH actions from Cirrusgatecat2022-04-0810-29/+299
* mistral: Updated CLK mux select namegatecat2022-03-181-1/+1
* Merge pull request #953 from YosysHQ/gatecat/mistral-updatesgatecat2022-03-181-1/+1
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| * mistral: Update to latest upstreamgatecat2022-03-171-1/+1
* | ci: Fixes for latest RapidWrightgatecat2022-03-172-2/+3
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* Mistral: fix gpio OE, add hmc bypass supportOlivier Galibert2022-01-181-1/+1
* Sync with the current state of mistralOlivier Galibert2022-01-181-1/+1
* mistral: Update to latest enum namegatecat2021-12-221-1/+1
* mistral: Bump CI versiongatecat2021-12-121-1/+1
* mistral: Add 'tools' dir to include pathgatecat2021-12-111-1/+1
* mistral: Sync with yet another reorganizationOlivier Galibert2021-10-281-1/+1
* interchange: Bump prjoxide versiongatecat2021-10-201-1/+1
* mistral: Use the iteratorsOlivier Galibert2021-10-191-1/+1
* Sync mistral version in CIOlivier Galibert2021-10-171-1/+1
* ci: Enable -Werror for interchange archgatecat2021-09-281-1/+1
* Update python-fpga-interchange to v0.0.20Maciej Dudek2021-09-231-1/+1
* gh: interchange: bump python-interchange tagAlessandro Comodi2021-08-311-1/+1
* mistral: Include mistral generated files in include dirsgatecat2021-08-151-1/+1
* [interchange] Update chipdb and python-fpga-interchange versionsMaciej Dudek2021-07-141-1/+1
* interchange: bump python-interchange versionAlessandro Comodi2021-07-081-1/+1
* ci: remove RapidWright patchingAlessandro Comodi2021-06-241-3/+0
* interchange: Bump versionsgatecat2021-06-151-2/+2
* interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
* interchange: ci: update python-interchange tagAlessandro Comodi2021-06-111-1/+1
* ci: Bump mistral versiongatecat2021-06-052-6/+2
* Remove redundant code after hashlib movegatecat2021-06-021-1/+1
* interchange: Add LIFCL-40 EVN testsgatecat2021-06-012-3/+3
* interchange: Bump versionsgatecat2021-05-271-1/+1
* interchange: Bump versionsgatecat2021-05-211-1/+1
* gh-actions: interchange: use commit sha as cache keyAlessandro Comodi2021-05-201-4/+10
* ci: Use GH only for Mistral and fpga-interchangegatecat2021-05-152-0/+57
* interchange: Bump versiongatecat2021-05-071-1/+1
* interchange: Bump versionsgatecat2021-04-301-2/+2
* interchange: Bump versionsgatecat2021-04-201-1/+1
* Merge pull request #678 from acomodi/initial-fasm-generationgatecat2021-04-141-1/+1
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| * gh-actions: increase python-fpga-interchange tag versionAlessandro Comodi2021-04-141-1/+1
* | ci: Re-enable abseil for interchange CIgatecat2021-04-141-1/+1
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* interchange: Pin prjoxide commitgatecat2021-04-092-0/+3
* Don't fail-fast for GH actions to allow for easier CI debugging.Keith Rothman2021-04-061-0/+3
* [interchange] Update interchange CI for new chipdb change.Keith Rothman2021-04-012-3/+2
* interchange: Fix nexus cmake review commentsgatecat2021-03-311-7/+7
* ci: Build prjoxide only for LIFCLgatecat2021-03-302-7/+8
* interchange: Add Nexus LUT testgatecat2021-03-301-1/+1
* interchange: Add Nexus to CIgatecat2021-03-302-1/+10
* gh-actions: better yosys caching based on versionAlessandro Comodi2021-03-262-6/+35
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 01:02:23 +0000