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| * | Add missing router1 ctx->yield() callsClifford Wolf2018-11-201-0/+2
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #131 from smunaut/ice40_fixesDavid Shah2018-11-2010-167/+422
|\ \ | | | | | | iCE40: Bug fixes and general improvement of global network support
| * | ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-195-2/+58
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Add global network output support for LFOSC/HFOSCSylvain Munaut2018-11-191-2/+10
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/pack: Add helper to constain cells that are unique in the FPGASylvain Munaut2018-11-191-0/+16
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Add support for SB_GB_IOSylvain Munaut2018-11-195-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-192-84/+73
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-195-2/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/chipdb: Add wires to global network for all cells that can drive itSylvain Munaut2018-11-193-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | The icebox DB is a bit inconsistent in how global network connections are represented. Here we make it appear consistent by creating ports on the cells that can drive it. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-192-37/+63
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Fix BEL validity check for PLL vs SB_IOSylvain Munaut2018-11-191-21/+20
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Improve the is_sb_pll40_XXX predicates collectionSylvain Munaut2018-11-191-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Add a test for dual output PLL variant - Make them handle the packet version of the cell This will become useful for various tests during PLL rework Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Fix PLLTYPE for SB_PLL40_2F_PADSylvain Munaut2018-11-191-1/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/pll: Add proper support for PLLOUT_SELECT_xxx attributesSylvain Munaut2018-11-191-0/+18
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Make PLL default FEEDBACK_MODE to SIMPLESylvain Munaut2018-11-191-1/+1
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Minor fix in predicate checking for logic portSylvain Munaut2018-11-191-2/+3
| | | | | | | | | | | | | | | | | | | | | - is_sb_pll40 covers all the PLL types - Use helper to test for gbuf Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/pack: Stop looking for BEL when we have one during PLL placementSylvain Munaut2018-11-191-0/+1
| | | | | | | | | | | | | | | | | | | | | Ideally we should first process all the PLL that are constrained somehow (either explicitely or because they are PAD) and then free place the rest. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/pack: Allow PLL to be constrained via 'BEL' attributesSylvain Munaut2018-11-191-0/+10
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-192-0/+21
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #130 from smunaut/issue_127David Shah2018-11-202-8/+21
|\ \ \ | | | | | | | | common/placer1: In random pick, only use grid if there is more than 64 BELs
| * | | common/placer1: In random pick, only use grid if there is more than 64 BELsSylvain Munaut2018-11-192-8/+21
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | If you have a large grid and very few BELs of a given type, picking a random grid location yields very little odds of finding a BEL of that type. So for those, just put all of them at (0,0) and do a true random pick. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #132 from maikmerten/masterDavid Shah2018-11-201-0/+10
|\ \ \ | |/ / |/| | add "randomize-seed" command-line option
| * | add "randomize-seed" command-line optionMaik Merten2018-11-191-0/+10
|/ /
* | Merge pull request #124 from smunaut/ice40_warn_sbio_misuseDavid Shah2018-11-161-0/+5
|\ \ | | | | | | ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhere
| * | ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
|/ / | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #123 from smunaut/ice40_fix_line_endingsDavid Shah2018-11-161-1043/+1043
|\ \ | |/ |/| ice40/bitstream: Convert to UNIX line endings
| * ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
|/ | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* clangformatDavid Shah2018-11-1613-296/+463
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
| | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #119 from cr1901/win-fixDavid Shah2018-11-164-2/+6
|\ | | | | nextpnr-ecp5 Windows Fixes
| * Use native PATH environment-variable separator on Windows for PYTHONPATH. ↵William D. Jones2018-11-031-0/+4
| | | | | | | | | | | | Fixes 'Bad address' error in cmake. Signed-off-by: William D. Jones <thor0505@comcast.net>
| * Rename io.{h,cc} to pio.{h,cc} to avoid naming conflict with ↵William D. Jones2018-11-033-2/+2
| | | | | | | | | | | | Windows-provided io.h. Signed-off-by: William D. Jones <thor0505@comcast.net>
* | Merge pull request #118 from daveshah1/dcuDavid Shah2018-11-169-39/+935
|\ \ | | | | | | Adding ECP5 DCU support
| * | ecp5: Better use of BoostDavid Shah2018-11-161-3/+3
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Regression fix & formatDavid Shah2018-11-152-4/+14
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Support LOC attribute on DCUsDavid Shah2018-11-151-1/+25
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Add DCU availability checkDavid Shah2018-11-151-0/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Add timing info for SERDESDavid Shah2018-11-151-1/+26
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: DCU clocking fixesDavid Shah2018-11-151-2/+8
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: EXTREFB fixesDavid Shah2018-11-152-1/+5
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: clangformatDavid Shah2018-11-152-18/+23
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Trim IO connected to top level portsDavid Shah2018-11-151-15/+73
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Adding ancillary DCU belsDavid Shah2018-11-154-1/+57
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: remove debug and clangformatDavid Shah2018-11-153-10/+13
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | dcu: Fix bitstream param handlingDavid Shah2018-11-151-0/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Prefer DCCs with dedicated routing when placing DCCsDavid Shah2018-11-151-0/+43
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | ecp5: Working on DCUDavid Shah2018-11-153-5/+63
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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