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Age
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*
interchange: Bump versions
gatecat
2021-04-20
2
-1
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+1
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interchange: Handle disconnected/missing cell pins
gatecat
2021-04-19
3
-6
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+56
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interchange: Add default cell connections to chipdb
gatecat
2021-04-19
1
-1
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+24
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Merge pull request #681 from YosysHQ/gatecat/more-pybindings
gatecat
2021-04-15
2
-0
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+8
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Add Python bindings for placement tests
gatecat
2021-04-15
2
-0
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+8
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Merge pull request #680 from YosysHQ/gatecat/fix-util
gatecat
2021-04-15
1
-2
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+2
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Fix utilisation report when bel buckets are used
gatecat
2021-04-15
1
-2
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+2
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Merge pull request #678 from acomodi/initial-fasm-generation
gatecat
2021-04-14
21
-71
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+136
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gh-actions: increase python-fpga-interchange tag version
Alessandro Comodi
2021-04-14
1
-1
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+1
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interchange: add FASM generation target and clean-up tests
Alessandro Comodi
2021-04-14
20
-70
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+135
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Merge pull request #679 from YosysHQ/gatecat/disable-absl
gatecat
2021-04-14
11
-63
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+54
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ci: Re-enable abseil for interchange CI
gatecat
2021-04-14
1
-1
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+1
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Hash table refactoring
gatecat
2021-04-14
10
-62
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+53
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Merge pull request #677 from YosysHQ/gatecat/ppip-no-input
gatecat
2021-04-13
1
-14
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+35
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interchange: Allow pseudo-cells with no input pins
gatecat
2021-04-13
1
-14
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+35
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Merge pull request #676 from YosysHQ/gatecat/fix-sta-crash
gatecat
2021-04-13
2
-58
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+73
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timing: Fix domain init when loops are present
gatecat
2021-04-13
2
-58
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+73
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Merge pull request #674 from adamgreig/heap-spreader-fix
gatecat
2021-04-12
1
-0
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+4
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HeAP: Skip high-strength cells in both cell loops.
Adam Greig
2021-04-12
1
-0
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+4
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Merge pull request #673 from YosysHQ/gatecat/fix-fast-bels-ref
gatecat
2021-04-12
1
-14
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+18
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fast_bels: Don't return pointer that might become invalid
gatecat
2021-04-12
1
-14
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+18
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clangformat
gatecat
2021-04-12
8
-133
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+134
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Merge pull request #668 from YosysHQ/gatecat/cell-bel-name-vcc
gatecat
2021-04-09
1
-6
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+10
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interchange: Disambiguate cell and bel pins when creating Vcc ties
gatecat
2021-04-09
1
-6
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+10
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Merge pull request #669 from YosysHQ/gatecat/prjoxide-pin
gatecat
2021-04-09
2
-0
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+3
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interchange: Pin prjoxide commit
gatecat
2021-04-09
2
-0
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+3
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Merge pull request #667 from YosysHQ/fix_qt
Miodrag Milanović
2021-04-08
1
-0
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+4
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Add same fix as in issue #373
Miodrag Milanovic
2021-04-08
1
-0
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+4
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Merge pull request #665 from cr1901/optional-lto
gatecat
2021-04-07
1
-2
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+13
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Add CMake option to enable IPO (enabled by default).
William D. Jones
2021-04-07
1
-2
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+13
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Merge pull request #659 from litghost/pseudo_pip_fixes
gatecat
2021-04-06
11
-66
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+882
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[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.
Keith Rothman
2021-04-06
1
-1
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+16
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Don't fail-fast for GH actions to allow for easier CI debugging.
Keith Rothman
2021-04-06
1
-0
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+3
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[interchange] Remove requirement to have wire_lut.
Keith Rothman
2021-04-06
3
-6
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+7
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[interchange] Fix invalid use of local variables due to refactoring.
Keith Rothman
2021-04-06
3
-6
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+7
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[interchange] Prevent site router from generating incorrect LUTs.
Keith Rothman
2021-04-06
3
-42
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+102
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[interchange] Scale edge cost of pseudo pips.
Keith Rothman
2021-04-06
2
-5
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+12
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[interchange] Fix missing inline methods in site_arch.impl.h
Keith Rothman
2021-04-06
2
-8
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+9
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[interchange] Disallow site edges during general routing.
Keith Rothman
2021-04-06
2
-5
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+23
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[interchange] Add crude pseudo pip model.
Keith Rothman
2021-04-06
6
-7
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+717
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Merge pull request #663 from litghost/fix_router2_without_bb
gatecat
2021-04-06
1
-1
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+13
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Fix bug in router2 where router may give up too early.
Keith Rothman
2021-04-06
1
-1
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+13
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Merge pull request #661 from litghost/document_site_router
gatecat
2021-04-06
1
-10
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+58
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[interchange] Add some documentation for the site router.
Keith Rothman
2021-04-05
1
-10
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+58
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Merge pull request #662 from litghost/fix_cirrus_ci
gatecat
2021-04-06
1
-1
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+1
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Increase vCPU to 5 because of cirrus resource limit change.
Keith Rothman
2021-04-05
1
-1
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+1
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Merge pull request #657 from acomodi/interchange-counter-multi-board
gatecat
2021-04-06
5
-23
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+25
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interchange: counter: testing on multiple boards
Alessandro Comodi
2021-04-01
5
-23
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+25
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Merge pull request #658 from litghost/increment_chipdb
gatecat
2021-04-02
5
-5
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+14
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[interchange] Update interchange CI for new chipdb change.
Keith Rothman
2021-04-01
2
-3
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+2
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