| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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nexus: Hotfix to disable unimplemented DCS routethru
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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gowin: Add GUI.
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All internal constants for describing the graphics have been moved
to the .cc file.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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* Items such as LUT, DFF, MUX, ALU, IOB are displayed;
* Local wires, 1-2-4-8 wires are displayed;
* The clock spines, taps and branches are displayed with some caveats.
For now, you can not create a project in the GUI because of possible
conflict with another PR (about GW1NR-9C support), but you can specify
the board in the command line and load .JSON and .CST in the GUI.
Although ALUs are displayed, but the CIN and COUT wires are not. This is
still an unsolved problem.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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For differential signals it is necessary to set the position of two pins
at once: P and N.
This commit adds that capability and also adds another style of location
setting --- with the pin letter in square brackets used in vendor tools.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Honor nexus OSCA frequency tolerance (corrected)
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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nexus: arch: add option to adjust the estimation delay multiplication factor
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Honor nexus OSCA frequency tolerance
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Fix for Nexus DSP packing
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macro
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Sync with the current state of mistral
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ice40: Pack LUT at start of carry chain if there is 1 candidate
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Signed-off-by: gatecat <gatecat@ds0.me>
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Better hashing function for integer pairs
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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Viaduct API for a hybrid between generic and full-custom arch
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Signed-off-by: gatecat <gatecat@ds0.me>
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gowin: Fix last MUX2_LUT8
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In fact, there is also an input/output column.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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SSOArray: Implement move and assignment operators
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Signed-off-by: gatecat <gatecat@ds0.me>
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generic: Refactor for faster performance
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This won't affect Python-built arches significantly; but will be useful
for the future 'viaduct' functionality where generic routing graphs can
be built on the C++ side; too.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Add support for GW1NS-4 series devices
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gowin: Initializing the grid dimensions
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gridDimX and gridDimY are not initialized explicitly, which leads to
effects when the design is reloaded, say, from the GUI.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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gowin: Add simplified IO cells processing
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Some models have I/O cells that are IOBUFs, and other types (IBUFs and
OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done
with general-purpose routing so it's best to do it here to avoid
conflicts.
For this purpose, in the new bases, these special cells are of type IOBS
(IOB Simplified).
The proposed changes are compatible with bases of previous versions of
Apycula and do not require changing .CST constraint files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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mistral: Update to latest enum name
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Signed-off-by: gatecat <gatecat@ds0.me>
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nexus: handle SLEWRATE in pdc
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archapi: Use arbitrary rather than actual placement in predictDelay [breaking change]
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This makes predictDelay be based on an arbitrary belpin pair rather
than a arc of a net based on cell placement. This way 'what-if'
decisions can be evaluated without actually changing placement;
potentially useful for parallel placement.
A new helper predictArcDelay behaves like the old predictDelay to
minimise the impact on existing passes; only arches need be updated.
Signed-off-by: gatecat <gatecat@ds0.me>
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