Merge pull request #895 from galibert/master

Sync with the current state of mistral

6 files changed, 83 insertions, 229 deletions

diff --git a/.github/workflows/mistral_ci.yml b/.github/workflows/mistral_ci.yml
index 64300d78..a02026cf 100644
--- a/.github/workflows/mistral_ci.yml
+++ b/.github/workflows/mistral_ci.yml
@@ -21,7 +21,7 @@ jobs:
     - name: Execute build nextpnr
       env:
         MISTRAL_PATH: ${{ github.workspace }}/deps/mistral
-        MISTRAL_REVISION: e039b595529ab573d9cb01c64ef927f9d81d63ce
+        MISTRAL_REVISION: 0c2ab2b2c6af33fea1c20349be2e0068366ed615 
       run: |
         source ./.github/ci/build_mistral.sh
         get_dependencies
diff --git a/mistral/arch.cc b/mistral/arch.cc
index 034ecb98..f61d07ab 100644
--- a/mistral/arch.cc
+++ b/mistral/arch.cc
@@ -43,6 +43,42 @@ void IdString::initialize_arch(const BaseCtx *ctx)
 #undef X
 }
 
+CycloneV::rnode_t Arch::find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi, int pi) const
+{
+    auto pn1 = CycloneV::pnode(bt, x, y, port, bi, pi);
+    auto rn1 = cyclonev->pnode_to_rnode(pn1);
+    if(rn1)
+        return rn1;
+
+    if(bt == CycloneV::GPIO) {
+        auto pn2 = cyclonev->p2p_to(pn1);
+        if(!pn2) {
+            auto pnv = cyclonev->p2p_from(pn1);
+            if(!pnv.empty())
+                pn2 = pnv[0];
+        }
+        auto pn3 = cyclonev->hmc_get_bypass(pn2);
+        auto rn2 = cyclonev->pnode_to_rnode(pn3);
+        return rn2;
+    }
+
+    return 0;
+}
+
+WireId Arch::get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
+{
+    auto rn = find_rnode(bt, x, y, port, bi, pi);
+    if(rn)
+        return WireId(rn);
+    
+    log_error("Trying to connect unknown node %s\n", CycloneV::pn2s(CycloneV::pnode(bt, x, y, port, bi, pi)).c_str());
+}
+
+bool Arch::has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi) const
+{
+    return find_rnode(bt, x, y, port, bi, pi) != 0;
+}
+
 Arch::Arch(ArchArgs args)
 {
     this->args = args;
diff --git a/mistral/arch.h b/mistral/arch.h
index 471b5251..e931df2d 100644
--- a/mistral/arch.h
+++ b/mistral/arch.h
@@ -461,10 +461,9 @@ struct Arch : BaseArch<ArchRanges>
 
     void add_bel_pin(BelId bel, IdString pin, PortType dir, WireId wire);
 
-    WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const
-    {
-        return WireId(cyclonev->pnode_to_rnode(CycloneV::pnode(bt, x, y, port, bi, pi)));
-    }
+    CycloneV::rnode_t find_rnode(CycloneV::block_type_t bt, int x, int y, CycloneV::port_type_t port, int bi = -1, int pi = -1) const;
+    WireId get_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
+    bool has_port(CycloneV::block_type_t bt, int x, int y, int bi, CycloneV::port_type_t port, int pi = -1) const;
 
     void create_lab(int x, int y, bool is_mlab);       // lab.cc
     void create_gpio(int x, int y);                    // io.cc
@@ -562,7 +561,6 @@ struct Arch : BaseArch<ArchRanges>
 
     // -------------------------------------------------
 
-    void init_base_bitstream(); // base_bitstream.cc
     void build_bitstream();     // bitstream.cc
 };
 
diff --git a/mistral/base_bitstream.cc b/mistral/base_bitstream.cc
deleted file mode 100644
index 9fa74fb9..00000000
--- a/mistral/base_bitstream.cc
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *  nextpnr -- Next Generation Place and Route
- *
- *  Copyright (C) 2021  gatecat <gatecat@ds0.me>
- *
- *  Permission to use, copy, modify, and/or distribute this software for any
- *  purpose with or without fee is hereby granted, provided that the above
- *  copyright notice and this permission notice appear in all copies.
- *
- *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "log.h"
-#include "nextpnr.h"
-
-NEXTPNR_NAMESPACE_BEGIN
-
-namespace {
-// Device-specific default config for the sx120f die
-void default_sx120f(CycloneV *cv)
-{
-    // Default PMA config?
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::TRISTATE);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 11), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::TRISTATE);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::DOWN);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 23), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 0, CycloneV::UP);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FFPLL_IQCLK_DIRECTION, 1, CycloneV::UP);
-    cv->bmux_b_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::FPLL_DRV_EN, 0, 0);
-    cv->bmux_m_set(CycloneV::PMA3, CycloneV::xy2pos(0, 35), CycloneV::HCLK_TOP_OUT_DRIVER, 0, CycloneV::TRISTATE);
-    // Default PLL config
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN0_PRECOMP, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_ATB_EN1_PRECOMP, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_BG_KICKSTART, 0, 1);
-    cv->bmux_b_set(CycloneV::FPLL, CycloneV::xy2pos(0, 73), CycloneV::PL_AUX_VBGMON_POWERDOWN, 0, 1);
-    // Default TERM config
-    cv->bmux_b_set(CycloneV::TERM, CycloneV::xy2pos(89, 34), CycloneV::INTOSC_2_EN, 0, 0);
-
-    // TODO: what if these pins are used? where do these come from
-    for (int z = 0; z < 4; z++) {
-        cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 43), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
-        cv->bmux_m_set(CycloneV::GPIO, CycloneV::xy2pos(89, 66), CycloneV::IOCSR_STD, z, CycloneV::NVR_LOW);
-    }
-    for (int y : {38, 44, 51, 58, 65, 73, 79}) {
-        // TODO: Why only these upper DQS? is there a pattern?
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_2X_CLK_DQS_INV, 0, 1);
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_ACLR_LFIFO_EN, 0, 1);
-        cv->bmux_b_set(CycloneV::DQS16, CycloneV::xy2pos(89, y), CycloneV::RB_LFIFO_BYPASS, 0, 0);
-    }
-
-    // Discover these mux values using
-    //   grep 'i [_A-Z0-9.]* 1' empty.bt
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 12), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 13), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 34), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 35), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 37), 31), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 40), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 46), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 47), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 53), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 54), 4), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(0, 73), 68), true);
-
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 18), 66), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 20), 8), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 27), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 28), 43), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 59), 66), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 61), 8), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 68), 69), true);
-    cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(9, 69), 43), true);
-
-    for (int z = 10; z <= 45; z++)
-        cv->inv_set(CycloneV::rnode(CycloneV::GOUT, CycloneV::xy2pos(51, 80), z), true);
-}
-} // namespace
-
-void Arch::init_base_bitstream()
-{
-    switch (cyclonev->current_model()->variant.die.type) {
-    case CycloneV::SX120F:
-        default_sx120f(cyclonev);
-        break;
-    default:
-        log_error("FIXME: die type %s currently unsupported for bitgen.\n",
-                  cyclonev->current_model()->variant.die.name);
-    }
-}
-
-NEXTPNR_NAMESPACE_END
diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc
index eed508b3..340f4b96 100644
--- a/mistral/bitstream.cc
+++ b/mistral/bitstream.cc
@@ -29,129 +29,41 @@ struct MistralBitgen
     Context *ctx;
     CycloneV *cv;
 
-    void init()
-    {
-        ctx->init_base_bitstream();
-        // Default options
-        cv->opt_b_set(CycloneV::ALLOW_DEVICE_WIDE_OUTPUT_ENABLE_DIS, true);
-        if (!ctx->setting<bool>("compress_rbf", false))
-            cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
-        cv->opt_n_set(CycloneV::CRC_DIVIDE_ORDER, 8);
-        cv->opt_b_set(CycloneV::CVP_CONF_DONE_EN, true);
-        cv->opt_b_set(CycloneV::DEVICE_WIDE_RESET_EN, true);
-        cv->opt_n_set(CycloneV::DRIVE_STRENGTH, 8);
-        cv->opt_b_set(CycloneV::IOCSR_READY_FROM_CSR_DONE_EN, true);
-        cv->opt_b_set(CycloneV::NCEO_DIS, true);
-        cv->opt_b_set(CycloneV::OCT_DONE_DIS, true);
-        cv->opt_r_set(CycloneV::OPT_A, 0x1dff);
-        if (!ctx->setting<bool>("compress_rbf", false))
-            cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
-        else
-            cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
-        cv->opt_b_set(CycloneV::RELEASE_CLEARS_BEFORE_TRISTATES_DIS, true);
-        cv->opt_b_set(CycloneV::RETRY_CONFIG_ON_ERROR_EN, true);
-        cv->opt_r_set(CycloneV::START_UP_CLOCK, 0x3F);
-        // Default inversion
-        write_default_inv();
-    }
+    using rnode_t = CycloneV::rnode_t;
+    using pnode_t = CycloneV::pnode_t;
+    using pos_t = CycloneV::pos_t;
+    using block_type_t = CycloneV::block_type_t;
+    using port_type_t = CycloneV::port_type_t;
 
-    void write_default_inv()
+    rnode_t find_rnode(block_type_t bt, pos_t pos, port_type_t port, int bi = -1, int pi = -1) const
     {
-        // Some PNODEs are inverted by default. Set them up here.
-        for (const auto &pn2r : cv->get_all_p2r()) {
-            const auto &pn = pn2r.first;
-            auto pt = CycloneV::pn2pt(pn);
-            auto pi = CycloneV::pn2pi(pn);
+        auto pn1 = CycloneV::pnode(bt, pos, port, bi, pi);
+        auto rn1 = cv->pnode_to_rnode(pn1);
+        if(rn1)
+            return rn1;
 
-            switch (CycloneV::pn2bt(pn)) {
-            case CycloneV::HMC: {
-                // HMC OE are inverted to set OE=0, i.e. unused pins floating
-                // TODO: handle the case when we are using the HMC or HMC bypass
-                std::string name(CycloneV::port_type_names[pt]);
-                if (name.compare(0, 5, "IOINT") != 0 || name.compare(name.size() - 2, 2, "OE") != 0)
-                    continue;
-                cv->inv_set(pn2r.second, true);
-                break;
-            };
-            // HPS IO - TODO: what about when we actually support the HPS primitives?
-            case CycloneV::HPS_BOOT: {
-                switch (pt) {
-                case CycloneV::CSEL_EN:
-                case CycloneV::BSEL_EN:
-                case CycloneV::BOOT_FROM_FPGA_READY:
-                case CycloneV::BOOT_FROM_FPGA_ON_FAILURE:
-                    cv->inv_set(pn2r.second, true);
-                    break;
-                case CycloneV::CSEL:
-                    if (pi < 2)
-                        cv->inv_set(pn2r.second, true);
-                    break;
-                case CycloneV::BSEL:
-                    if (pi < 3)
-                        cv->inv_set(pn2r.second, true);
-                    break;
-                default:
-                    break;
-                };
-                break;
-            };
-            case CycloneV::HPS_CROSS_TRIGGER: {
-                if (pt == CycloneV::CLK_EN)
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::HPS_TEST: {
-                if (pt == CycloneV::CFG_DFX_BYPASS_ENABLE)
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::GPIO: {
-                // Ignore GPIO used by the design
-                BelId bel = ctx->bel_by_block_idx(CycloneV::pn2x(pn), CycloneV::pn2y(pn), id_MISTRAL_IO,
-                                                  CycloneV::pn2bi(pn));
-                if (bel != BelId() && ctx->getBoundBelCell(bel) != nullptr)
-                    continue;
-                // Bonded IO invert OEIN.1 which disables the output buffer and floats the IO
-                // Unbonded IO invert OEIN.0 which enables the output buffer, and {DATAIN.[0123]} to drive a constant
-                // GND, presumably for power/EMI reasons
-                bool is_bonded = cv->pin_find_pnode(pn) != nullptr;
-                if (is_bonded && (pt != CycloneV::OEIN || pi != 1))
-                    continue;
-                if (!is_bonded && (pt != CycloneV::DATAIN) && (pt != CycloneV::OEIN || pi != 0))
-                    continue;
-                cv->inv_set(pn2r.second, true);
-                break;
-            };
-            case CycloneV::FPLL: {
-                if (pt == CycloneV::EXTSWITCH0 || (pt == CycloneV::CLKEN && pi < 2))
-                    cv->inv_set(pn2r.second, true);
-                break;
-            };
-            default:
-                break;
+        if(bt == CycloneV::GPIO) {
+            auto pn2 = cv->p2p_to(pn1);
+            if(!pn2) {
+                auto pnv = cv->p2p_from(pn1);
+                if(!pnv.empty())
+                    pn2 = pnv[0];
             }
+            auto pn3 = cv->hmc_get_bypass(pn2);
+            auto rn2 = cv->pnode_to_rnode(pn3);
+            return rn2;
         }
+
+        return 0;
     }
 
-    void write_dqs()
+    void options()
     {
-        for (auto pos : cv->dqs16_get_pos()) {
-            int x = CycloneV::pos2x(pos), y = CycloneV::pos2y(pos);
-            // DQS bypass for used output pins
-            for (int z = 0; z < 16; z++) {
-                int ioy = y + (z / 4) - 2;
-                if (ioy < 0 || ioy >= int(cv->get_tile_sy()))
-                    continue;
-                BelId bel = ctx->bel_by_block_idx(x, ioy, id_MISTRAL_IO, z % 4);
-                if (bel == BelId())
-                    continue;
-                CellInfo *ci = ctx->getBoundBelCell(bel);
-                if (ci == nullptr || (ci->type != id_MISTRAL_IO && ci->type != id_MISTRAL_OB))
-                    continue; // not an output
-                cv->bmux_m_set(CycloneV::DQS16, pos, CycloneV::INPUT_REG4_SEL, z, CycloneV::SEL_LOCKED_DPA);
-                cv->bmux_r_set(CycloneV::DQS16, pos, CycloneV::RB_T9_SEL_EREG_CFF_DELAY, z, 0x1f);
-            }
-        }
+        if (!ctx->setting<bool>("compress_rbf", false)) {
+            cv->opt_b_set(CycloneV::COMPRESSION_DIS, true);
+            cv->opt_r_set(CycloneV::OPT_B, 0xffffff40adffffffULL);
+        } else
+            cv->opt_r_set(CycloneV::OPT_B, 0xffffff402dffffffULL);
     }
 
     void write_routing()
@@ -182,12 +94,19 @@ struct MistralBitgen
         if (is_output) {
             cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::DRIVE_STRENGTH, bi, CycloneV::V3P3_LVTTL_16MA_LVCMOS_2MA);
             cv->bmux_m_set(CycloneV::GPIO, pos, CycloneV::IOCSR_STD, bi, CycloneV::DIS);
+
+            // Output gpios must also bypass things in the associated dqs
+            auto dqs = cv->p2p_to(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::PNONE, bi, -1));
+            if(dqs) {
+                cv->bmux_m_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::INPUT_REG4_SEL, CycloneV::pn2bi(dqs), CycloneV::SEL_LOCKED_DPA);
+                cv->bmux_r_set(CycloneV::DQS16, CycloneV::pn2p(dqs), CycloneV::RB_T9_SEL_EREG_CFF_DELAY, CycloneV::pn2bi(dqs), 0x1f);
+            }
         }
         // There seem to be two mirrored OEIN inversion bits for constant OE for inputs/outputs. This might be to
         // prevent a single bitflip from turning inputs to outputs and messing up other devices on the boards, notably
         // ECP5 does similar. OEIN.0 inverted for outputs; OEIN.1 for inputs
-        cv->inv_set(cv->pnode_to_rnode(CycloneV::pnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, is_output ? 0 : 1)),
-                    true);
+        cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 0), is_output);
+        cv->inv_set(find_rnode(CycloneV::GPIO, pos, CycloneV::OEIN, bi, 1), !is_output);
     }
 
     void write_clkbuf_cell(CellInfo *ci, int x, int y, int bi)
@@ -392,9 +311,8 @@ struct MistralBitgen
     void run()
     {
         cv->clear();
-        init();
+        options();
         write_routing();
-        write_dqs();
         write_cells();
         write_labs();
     }
diff --git a/mistral/io.cc b/mistral/io.cc
index dab3672e..a0a01af3 100644
--- a/mistral/io.cc
+++ b/mistral/io.cc
@@ -30,10 +30,12 @@ void Arch::create_gpio(int x, int y)
         WireId pad = add_wire(x, y, id(stringf("PAD[%d]", z)));
         BelId bel = add_bel(x, y, id(stringf("IO[%d]", z)), id_MISTRAL_IO);
         add_bel_pin(bel, id_PAD, PORT_INOUT, pad);
-        // FIXME: is the port index of zero always correct?
-        add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
-        add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
-        add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+        if(has_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0)) {
+            // FIXME: is the port index of zero always correct?
+            add_bel_pin(bel, id_I, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAOUT, 0));
+            add_bel_pin(bel, id_OE, PORT_IN, get_port(CycloneV::GPIO, x, y, z, CycloneV::OEIN, 0));
+            add_bel_pin(bel, id_O, PORT_OUT, get_port(CycloneV::GPIO, x, y, z, CycloneV::DATAIN, 0));
+        }
         bel_data(bel).block_index = z;
     }
 }