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* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-1512-174/+272
|\ | | | | Support for cell pin to bel pin mappings
| * router2: Support for multiple bel pins per cell pingatecat2021-02-101-85/+95
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router1: Support for multiple bel pins per cell pingatecat2021-02-101-62/+78
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Start making use of getBelPinsForCellPin APIgatecat2021-02-106-38/+84
| | | | | | | | | | | | | | | | | | | | | | | | This replaces getNetinfoSinkWire with 3 new functions for different use cases. At the moment all existing code has been moved to getNetinfoSinkWire with phys_idx=0 so the build doesn't break; but this won't yet function properly with more than one sink. But it provides a base on which to work on refactoring the routers to support this case. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-107-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #582 from litghost/add_xdc_parsergatecat2021-02-128-4/+238
|\ \ | | | | | | Add XDC parser to FPGA interchange
| * | Add FPGA interchange tests to CI.Keith Rothman2021-02-121-1/+2
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Update tests to include XDC unit test.Keith Rothman2021-02-121-0/+0
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Run "make clangformat".Keith Rothman2021-02-124-66/+53
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Remove capnp and libz for XDC parser PR.Keith Rothman2021-02-121-4/+0
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-123-14/+52
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add unknown handles to convert [0] to "[0]".Keith Rothman2021-02-121-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Tcl reads something like "set port [get_ports x[0]]" as "invoke proc 0 with zero arguments", rather than just "[0]". To prevent exposing non-Tcl users this, "[<number>]" just return themselves. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add FPGA interchange XDC parser.Keith Rothman2021-02-125-3/+204
|/ / | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #579 from litghost/add_control_for_split_iogatecat2021-02-124-18/+28
|\ \ | | | | | | Add control to whether GenericFrontend splits IO ports.
| * | Update docs.Keith Rothman2021-02-121-0/+1
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add control to whether GenericFrontend splits IO ports.Keith Rothman2021-02-113-18/+27
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Make BaseArch getDecalGraphics return an empty rangegatecat2021-02-122-2/+2
| | | | | | | | | | | | | | | | | | | | | Fix assertion failure when opening the GUI on an arch without any decals. Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #580 from litghost/add_design_loaded_state_variablegatecat2021-02-123-1/+8
|\ \ \ | | | | | | | | Add design_loaded state variable.
| * | | Add design_loaded state variable.Keith Rothman2021-02-113-1/+8
| |/ / | | | | | | | | | | | | | | | | | | This is to decouple the command line flag "--json" and enable other frontend's. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #581 from litghost/add_isbelhiddengatecat2021-02-1211-16/+30
|\ \ \ | |/ / |/| | Add getBelHidden and add some missing "override" statements.
| * | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-1111-16/+30
|/ / | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #574 from YosysHQ/gatecat/belpin-1gatecat2021-02-104-37/+0
|\| | | | | Remove the unused CellInfo::pins field
| * Remove the unused CellInfo::pins fieldgatecat2021-02-104-37/+0
|/ | | | | | | | | | | No arches ever actually used this to implement a Cell->Bel pin mapping, and in practice if any did try they would inevitably hit bitrot. This field had limited use in practice as it is necessary to also support cases where one cell pin maps to more than one bel pin. Removing this old field is the first step towards developing a new API for this. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #573 from YosysHQ/gatecat/basearchrangesgatecat2021-02-095-49/+25
|\ | | | | Add BaseArchRanges for default ArchRanges types
| * Add BaseArchRanges for default ArchRanges typesgatecat2021-02-095-49/+25
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Add nextpnr-gowin binary to gitignoregatecat2021-02-091-0/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-0820-1145/+1334
|\ | | | | Create a new BaseArch that formally specifies the Arch API and provides some base implementations
| * Make BaseCtx destructor virtualgatecat2021-02-081-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Update docs with API changesD. Shah2021-02-081-21/+160
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * interchange: Base on ArchAPID. Shah2021-02-082-106/+135
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-086-147/+153
| | | | | | | | | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-057-11/+27
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * gowin: Switch to BaseArchD. Shah2021-02-052-150/+107
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * generic: Base upon ArchAPID. Shah2021-02-051-102/+132
| | | | | | | | | | | | | | As generic is often picked as our 'odd-one-out' we also use it as an example of an Arch that does not build upon BaseArch. Signed-off-by: D. Shah <dave@ds0.me>
| * nexus: Switch to BaseArchD. Shah2021-02-055-301/+103
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * ice40: Switch to BaseArchD. Shah2021-02-055-182/+115
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add pure-virtual ArchAPI interfaceD. Shah2021-02-051-104/+198
| | | | | | | | | | | | | | | | | | This splits out the pure-virtual definition of the architecture API into ArchAPI; leaving BaseArch to only provide default implementations (which can now be completely opted out of by deriving from ArchAPI instead of BaseArch). Signed-off-by: D. Shah <dave@ds0.me>
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-053-7/+7
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add default implementation of bel bucket functionsD. Shah2021-02-055-88/+94
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add default implementation of some range-returning functionsD. Shah2021-02-052-17/+27
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Add a few more functions to ArchBaseD. Shah2021-02-052-11/+18
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * ecp5: Use common wire/pip bindingD. Shah2021-02-052-83/+7
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * Fix now-illegal use of reinterpret_castD. Shah2021-02-051-3/+5
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nextpnr: Example of shared wire/bel/pip binding codeD. Shah2021-02-051-13/+106
| | | | | | | | | | | | Currently not actually being tested Signed-off-by: D. Shah <dave@ds0.me>
| * nextpnr: Use templates to specify range typesD. Shah2021-02-052-18/+67
| | | | | | | | Signed-off-by: D. Shah <dave@ds0.me>
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-052-84/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | This makes the Arch API clearer and also allows a base implementation of functions to reduce the amount of complexity to get a basic Arch up and running. Currently this only implements these for functions that don't return a range. Range-returning functions will require more work in order due to the current 'duck typing' approach (probably a struct that contains the range types combined with templating.) Signed-off-by: D. Shah <dave@ds0.me>
* | Update prjoxide URLD. Shah2021-02-082-4/+4
| | | | | | | | Signed-off-by: D. Shah <gatecat@ds0.me>
* | Merge pull request #572 from YosysHQ/dave/more-ssizeDavid Shah2021-02-084-23/+23
|\ \ | |/ |/| Use RelSlice::ssize instead of cast-to-int throughout
| * Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-084-23/+23
|/ | | | Signed-off-by: D. Shah <dave@ds0.me>
* Merge pull request #567 from litghost/initial_fpga_interchangeDavid Shah2021-02-0515-2/+2582
|\ | | | | Initial FPGA interchange arch
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