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* Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
|\ | | | | [FPGA interchange] Convert some string constants to IdString.
| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
| | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
|\ \ | | | | | | Initial inverter logic for FPGA interchange
| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
| | | | | | | | | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-238-44/+446
|\| | | |/ |/| Update parameter processing based on new DeviceResources metadata
| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-237-43/+415
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update latest version of FPGA interchange schema.Keith Rothman2021-03-231-1/+10
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #642 from YosysHQ/gatecat/missing-cell-pingatecat2021-03-231-0/+3
|\ \ | |/ |/| interchange: Add nice error for missing cell pins
| * interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #641 from litghost/initial_lookaheadgatecat2021-03-2315-13/+2689
|\ \ | |/ |/| Initial lookahead for FPGA interchange.
| * Initial lookahead for FPGA interchange.Keith Rothman2021-03-2315-13/+2689
|/ | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #638 from litghost/fixup_physical_netlist_writergatecat2021-03-221-11/+93
|\ | | | | Correct some bugs in writing of physical netlist w.r.t. site sources.
| * Correct some bugs in writing of physical netlist w.r.t. site sources.Keith Rothman2021-03-221-11/+93
| | | | | | | | | | | | | | Local site sources should have their driving BEL pin included in the net so that the site wire is driven by an output BEL pin. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #637 from litghost/refine_site_routergatecat2021-03-2217-588/+2745
|\ \ | | | | | | Refine site router
| * | Rework FPGA interchange site router.Keith Rothman2021-03-2212-571/+2617
| | | | | | | | | | | | | | | | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add missing dependencies to CMake targets.Keith Rothman2021-03-225-17/+128
| |/ | | | | | | | | | | | | - Add additional targets useful for various situations. - Have counter test use common remap.v file. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-223-0/+10
|\ \ | | | | | | Add getBelPinType to Python interface.
| * | Add getBelPinType to Python interface.Keith Rothman2021-03-223-0/+10
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #632 from litghost/add_check_pip_for_netgatecat2021-03-228-16/+30
|\ \ | |/ |/| Add "checkPipAvailForNet" to Arch API.
| * Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-228-16/+30
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #636 from litghost/add_pseudo_pip_datagatecat2021-03-224-7/+144
|\ | | | | Add pseudo pip data
| * Increment required python-fpga-interchange version.Keith Rothman2021-03-221-1/+1
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-223-6/+143
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #635 from litghost/refactor_headersgatecat2021-03-2210-891/+1292
|\ | | | | Refactor header structures in FPGA interchange Arch.
| * Update tests to include Tcl header order fix.Keith Rothman2021-03-191-0/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-199-891/+1292
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #633 from YosysHQ/gatecat/optional-ipogatecat2021-03-191-3/+4
|\ | | | | cmake: Use IPO only if supported
| * cmake: Use IPO only if supportedgatecat2021-03-191-3/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #631 from litghost/fixup_gui_dependenciesgatecat2021-03-183-4/+32
|\ | | | | Update root CMake with some additional features
| * Add option to link against "libprofiler".Keith Rothman2021-03-181-0/+4
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add IPO support for nextpnr, and have it enabled by default.Keith Rothman2021-03-181-0/+7
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fixup GUI link dependencies on headers from libraries.Keith Rothman2021-03-183-4/+21
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #630 from litghost/run_clangformatgatecat2021-03-184-4/+3
|\ \ | |/ |/| Run "make clangformat" to fix up master.
| * Run "make clangformat". to fix up master.Keith Rothman2021-03-184-4/+3
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #629 from litghost/move_hash_selection_to_headergatecat2021-03-182-8/+52
|\ | | | | Moving hash map/set type selection to header.
| * Moving hash map/set type selection to header.Keith Rothman2021-03-172-8/+52
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #619 from acomodi/add-cmake-infra-fpga-interchangegatecat2021-03-1745-215/+860
|\ | | | | Add CMake infrastructure for fpga interchange
| * fpga_interchange: temporarily disable failing testAlessandro Comodi2021-03-171-1/+2
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: minor fixes and comments additionAlessandro Comodi2021-03-163-22/+57
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: address review commentsAlessandro Comodi2021-03-1610-20/+96
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * github-actions: use capnp v0.8.0Alessandro Comodi2021-03-162-4/+4
| | | | | | | | | | | | This also updates the note in the README for the FPGA interchange Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * github-actions: pin python-fpga-interchange to tagAlessandro Comodi2021-03-161-1/+2
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * github-actions: add basic CI to test FPGA interchangeAlessandro Comodi2021-03-162-0/+74
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: re-add README with updated instructionsAlessandro Comodi2021-03-161-0/+69
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: tests: add techmap optional source fileAlessandro Comodi2021-03-164-3/+19
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: add bbasm step and archcheckAlessandro Comodi2021-03-167-41/+78
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: address review commentsAlessandro Comodi2021-03-164-32/+91
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: tests: added comment and fixed XDCAlessandro Comodi2021-03-1616-29/+74
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * fpga_interchange: chipdb: use generic patching functionAlessandro Comodi2021-03-163-41/+96
| | | | | | | | | | | | Also moved the RapidWright invocation script path under a CMake variable Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-19 14:05:04 +0000